git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-meson/gxbb.h

   1 /*
   2  * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __GXBB_H__
   8 #define __GXBB_H__
   9
  10 #define GXBB_FIRMWARE_MEM_SIZE  0x1000000
  11
  12 #define GXBB_AOBUS_BASE         0xc8100000
  13 #define GXBB_PERIPHS_BASE       0xc8834400
  14 #define GXBB_HIU_BASE           0xc883c000
  15 #define GXBB_ETH_BASE           0xc9410000
  16
  17 /* Always-On Peripherals registers */
  18 #define GXBB_AO_ADDR(off)       (GXBB_AOBUS_BASE + ((off) << 2))
  19
  20 #define GXBB_AO_SEC_GP_CFG0     GXBB_AO_ADDR(0x90)
  21 #define GXBB_AO_SEC_GP_CFG3     GXBB_AO_ADDR(0x93)
  22 #define GXBB_AO_SEC_GP_CFG4     GXBB_AO_ADDR(0x94)
  23 #define GXBB_AO_SEC_GP_CFG5     GXBB_AO_ADDR(0x95)
  24
  25 #define GXBB_AO_MEM_SIZE_MASK   0xFFFF0000
  26 #define GXBB_AO_MEM_SIZE_SHIFT  16
  27 #define GXBB_AO_BL31_RSVMEM_SIZE_MASK   0xFFFF0000
  28 #define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT  16
  29 #define GXBB_AO_BL32_RSVMEM_SIZE_MASK   0xFFFF
  30
  31 /* Peripherals registers */
  32 #define GXBB_PERIPHS_ADDR(off)  (GXBB_PERIPHS_BASE + ((off) << 2))
  33
  34 /* GPIO registers 0 to 6 */
  35 #define _GXBB_GPIO_OFF(n)       ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
  36 #define GXBB_GPIO_EN(n)         GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
  37 #define GXBB_GPIO_IN(n)         GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
  38 #define GXBB_GPIO_OUT(n)        GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
  39
  40 #define GXBB_ETH_REG_0          GXBB_PERIPHS_ADDR(0x50)
  41 #define GXBB_ETH_REG_1          GXBB_PERIPHS_ADDR(0x51)
  42 #define GXBB_ETH_REG_2          GXBB_PERIPHS_ADDR(0x56)
  43 #define GXBB_ETH_REG_3          GXBB_PERIPHS_ADDR(0x57)
  44
  45 #define GXBB_ETH_REG_0_PHY_INTF         BIT(0)
  46 #define GXBB_ETH_REG_0_TX_PHASE(x)      (((x) & 3) << 5)
  47 #define GXBB_ETH_REG_0_TX_RATIO(x)      (((x) & 7) << 7)
  48 #define GXBB_ETH_REG_0_PHY_CLK_EN       BIT(10)
  49 #define GXBB_ETH_REG_0_INVERT_RMII_CLK  BIT(11)
  50 #define GXBB_ETH_REG_0_CLK_EN           BIT(12)
  51
  52 /* HIU registers */
  53 #define GXBB_HIU_ADDR(off)      (GXBB_HIU_BASE + ((off) << 2))
  54
  55 #define GXBB_MEM_PD_REG_0       GXBB_HIU_ADDR(0x40)
  56
  57 /* Ethernet memory power domain */
  58 #define GXBB_MEM_PD_REG_0_ETH_MASK      (BIT(2) | BIT(3))
  59
  60 /* Clock gates */
  61 #define GXBB_GCLK_MPEG_0        GXBB_HIU_ADDR(0x50)
  62 #define GXBB_GCLK_MPEG_1        GXBB_HIU_ADDR(0x51)
  63 #define GXBB_GCLK_MPEG_2        GXBB_HIU_ADDR(0x52)
  64 #define GXBB_GCLK_MPEG_OTHER    GXBB_HIU_ADDR(0x53)
  65 #define GXBB_GCLK_MPEG_AO       GXBB_HIU_ADDR(0x54)
  66
  67 #define GXBB_GCLK_MPEG_0_I2C   BIT(9)
  68 #define GXBB_GCLK_MPEG_1_ETH    BIT(3)
  69
  70 #endif /* __GXBB_H__ */