1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
7 #define __ASM_ARCH_MX5_IMX_REGS_H__
11 #if defined(CONFIG_MX51)
12 #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
13 #define IPU_SOC_BASE_ADDR 0x40000000
14 #define IPU_SOC_OFFSET 0x1E000000
15 #define SPBA0_BASE_ADDR 0x70000000
16 #define AIPS1_BASE_ADDR 0x73F00000
17 #define AIPS2_BASE_ADDR 0x83F00000
18 #define CSD0_BASE_ADDR 0x90000000
19 #define CSD1_BASE_ADDR 0xA0000000
20 #define NFC_BASE_ADDR_AXI 0xCFFF0000
21 #define CS1_BASE_ADDR 0xB8000000
22 #elif defined(CONFIG_MX53)
23 #define IPU_SOC_BASE_ADDR 0x18000000
24 #define IPU_SOC_OFFSET 0x06000000
25 #define SPBA0_BASE_ADDR 0x50000000
26 #define AIPS1_BASE_ADDR 0x53F00000
27 #define AIPS2_BASE_ADDR 0x63F00000
28 #define CSD0_BASE_ADDR 0x70000000
29 #define CSD1_BASE_ADDR 0xB0000000
30 #define NFC_BASE_ADDR_AXI 0xF7FF0000
31 #define IRAM_BASE_ADDR 0xF8000000
32 #define CS1_BASE_ADDR 0xF4000000
33 #define SATA_BASE_ADDR 0x10000000
35 #error "CPU_TYPE not defined"
38 #define IRAM_SIZE 0x00020000 /* 128 KB */
41 * SPBA global module enabled #0
43 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
44 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
45 #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000)
46 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
47 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
48 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
49 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
50 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
51 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
52 #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
53 #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
54 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
59 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
60 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
61 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
62 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
63 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
64 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
65 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
66 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
67 #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
68 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
69 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
70 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
71 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
72 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
73 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
74 #define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000)
75 #define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000)
76 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
77 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
78 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
80 #if defined(CONFIG_MX53)
81 #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
82 #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
83 #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
84 #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
85 #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
90 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
91 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
92 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
94 #define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000)
96 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
97 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
98 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
99 #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
100 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
101 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
102 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
103 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
104 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
105 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
106 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
107 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
108 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
109 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
110 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
111 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
112 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
113 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
114 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
115 #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
116 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
117 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
118 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
119 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
120 #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
121 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
122 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
123 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
124 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
126 #if defined(CONFIG_MX53)
127 #define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
140 #define CREP (1 << 7)
141 #define BL(x) (((x) & 0x7) << 8)
143 #define BCD(x) (((x) & 0x3) << 12)
144 #define BCS(x) (((x) & 0x3) << 14)
145 #define DSZ(x) (((x) & 0x7) << 16)
147 #define CSREC(x) (((x) & 0x7) << 20)
148 #define AUS (1 << 23)
149 #define GBC(x) (((x) & 0x7) << 24)
151 #define PSZ(x) (((x) & 0x0f << 28)
156 #define ADH(x) (((x) & 0x3))
157 #define DAPS(x) (((x) & 0x0f << 4)
160 #define MUX16_BYP (1 << 12)
165 #define RCSN(x) (((x) & 0x7))
166 #define RCSA(x) (((x) & 0x7) << 4)
167 #define OEN(x) (((x) & 0x7) << 8)
168 #define OEA(x) (((x) & 0x7) << 12)
169 #define RADVN(x) (((x) & 0x7) << 16)
170 #define RAL (1 << 19)
171 #define RADVA(x) (((x) & 0x7) << 20)
172 #define RWSC(x) (((x) & 0x3f) << 24)
177 #define RBEN(x) (((x) & 0x7))
179 #define RBEA(x) (((x) & 0x7) << 4)
180 #define RL(x) (((x) & 0x3) << 8)
181 #define PAT(x) (((x) & 0x7) << 12)
182 #define APR (1 << 15)
187 #define WCSN(x) (((x) & 0x7))
188 #define WCSA(x) (((x) & 0x7) << 3)
189 #define WEN(x) (((x) & 0x7) << 6)
190 #define WEA(x) (((x) & 0x7) << 9)
191 #define WBEN(x) (((x) & 0x7) << 12)
192 #define WBEA(x) (((x) & 0x7) << 15)
193 #define WADVN(x) (((x) & 0x7) << 18)
194 #define WADVA(x) (((x) & 0x7) << 21)
195 #define WWSC(x) (((x) & 0x3f) << 24)
196 #define WBED1 (1 << 30)
197 #define WAL (1 << 31)
205 * CSPI register definitions
208 #define MXC_CSPICTRL_EN (1 << 0)
209 #define MXC_CSPICTRL_MODE (1 << 1)
210 #define MXC_CSPICTRL_XCH (1 << 2)
211 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
212 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
213 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
214 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
215 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
216 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
217 #define MXC_CSPICTRL_MAXBITS 0xfff
218 #define MXC_CSPICTRL_TC (1 << 7)
219 #define MXC_CSPICTRL_RXOVF (1 << 6)
220 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
221 #define MAX_SPI_BYTES 32
223 /* Bit position inside CTRL register to be associated with SS */
224 #define MXC_CSPICTRL_CHAN 18
226 /* Bit position inside CON register to be associated with SS */
227 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
228 #define MXC_CSPICON_POL 4 /* SCLK polarity */
229 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
230 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
231 #define MXC_SPI_BASE_ADDRESSES \
237 * Number of GPIO pins per port
239 #define GPIO_NUM_PIN 32
241 #define IIM_SREV 0x24
242 #define ROM_SI_REV 0x48
244 #define NFC_BUF_SIZE 0x1000
247 #define M4IF_FBPM0 0x40
248 #define M4IF_FIDBP 0x48
249 #define M4IF_GENP_WEIM_MM_MASK 0x00000001
250 #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
252 /* Assuming 24MHz input clock with doubler ON */
254 #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
255 #define DP_MFD_864 (180 - 1) /* PL Dither mode */
256 #define DP_MFN_864 180
257 #define DP_MFN_800_DIT 60 /* PL Dither mode */
259 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
260 #define DP_MFD_850 (48 - 1)
261 #define DP_MFN_850 41
263 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
264 #define DP_MFD_800 (3 - 1)
267 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
268 #define DP_MFD_700 (24 - 1)
271 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
272 #define DP_MFD_665 (96 - 1)
273 #define DP_MFN_665 89
275 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
276 #define DP_MFD_532 (24 - 1)
277 #define DP_MFN_532 13
279 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
280 #define DP_MFD_400 (3 - 1)
283 #define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
284 #define DP_MFD_455 (48 - 1)
285 #define DP_MFN_455 23
287 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
288 #define DP_MFD_216 (4 - 1)
291 #define IMX_IIM_BASE (IIM_BASE_ADDR)
293 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
294 #include <asm/types.h>
296 #define __REG(x) (*((volatile u32 *)(x)))
297 #define __REG16(x) (*((volatile u16 *)(x)))
298 #define __REG8(x) (*((volatile u8 *)(x)))
334 #if defined(CONFIG_MX53)
398 #if defined(CONFIG_MX51)
407 #elif defined(CONFIG_MX53)
418 #define IOMUXC_GPR2_BITMAP_SPWG 0
419 #define IOMUXC_GPR2_BITMAP_JEIDA 1
421 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
422 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
423 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \
424 IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
425 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \
426 IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
428 #define IOMUXC_GPR2_DATA_WIDTH_18 0
429 #define IOMUXC_GPR2_DATA_WIDTH_24 1
431 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
432 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
433 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \
434 IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
435 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \
436 IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
438 #define IOMUXC_GPR2_MODE_DISABLED 0
439 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
440 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3
442 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
443 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
444 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \
445 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
446 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \
447 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
448 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \
449 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
451 /* System Reset Controller (SRC) */
462 u32 lpscmr; /* 0x00 */
463 u32 lpsclr; /* 0x04 */
464 u32 lpsar; /* 0x08 */
465 u32 lpsmcr; /* 0x0c */
468 u32 lppdr; /* 0x18 */
470 u32 hpcmr; /* 0x20 */
471 u32 hpclr; /* 0x24 */
472 u32 hpamr; /* 0x28 */
473 u32 hpalr; /* 0x2c */
475 u32 hpisr; /* 0x34 */
476 u32 hpienr; /* 0x38 */
511 #if defined(CONFIG_MX51)
513 #elif defined(CONFIG_MX53)
518 struct fuse_bank0_regs {
522 #if defined(CONFIG_MX51)
524 #elif defined(CONFIG_MX53)
529 struct fuse_bank1_regs {
535 #if defined(CONFIG_MX53)
536 struct fuse_bank4_regs {
543 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
544 #define PWMCR_DOZEEN (1 << 24)
545 #define PWMCR_WAITEN (1 << 23)
546 #define PWMCR_DBGEN (1 << 22)
547 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
548 #define PWMCR_CLKSRC_IPG (1 << 16)
549 #define PWMCR_EN (1 << 0)
560 #endif /* __ASSEMBLER__*/
562 #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */