2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
24 #define __ASM_ARCH_MX5_IMX_REGS_H__
26 #if defined(CONFIG_MX51)
27 #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
28 #define IPU_CTRL_BASE_ADDR 0x40000000
29 #define SPBA0_BASE_ADDR 0x70000000
30 #define AIPS1_BASE_ADDR 0x73F00000
31 #define AIPS2_BASE_ADDR 0x83F00000
32 #define CSD0_BASE_ADDR 0x90000000
33 #define CSD1_BASE_ADDR 0xA0000000
34 #define NFC_BASE_ADDR_AXI 0xCFFF0000
35 #define CS1_BASE_ADDR 0xB8000000
36 #elif defined(CONFIG_MX53)
37 #define IPU_CTRL_BASE_ADDR 0x18000000
38 #define SPBA0_BASE_ADDR 0x50000000
39 #define AIPS1_BASE_ADDR 0x53F00000
40 #define AIPS2_BASE_ADDR 0x63F00000
41 #define CSD0_BASE_ADDR 0x70000000
42 #define CSD1_BASE_ADDR 0xB0000000
43 #define NFC_BASE_ADDR_AXI 0xF7FF0000
44 #define IRAM_BASE_ADDR 0xF8000000
45 #define CS1_BASE_ADDR 0xF4000000
47 #error "CPU_TYPE not defined"
50 #define IRAM_SIZE 0x00020000 /* 128 KB */
53 * SPBA global module enabled #0
55 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
56 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
57 #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
58 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
59 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
60 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
61 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
62 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
63 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
64 #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
65 #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
66 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
71 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
72 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
73 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
74 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
75 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
76 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
77 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
78 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
79 #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
80 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
81 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
82 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
83 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
84 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
85 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
86 #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
87 #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
88 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
89 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
90 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
92 #if defined(CONFIG_MX53)
93 #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
94 #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
95 #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
100 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
101 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
102 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
103 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
104 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
105 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
106 #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
107 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
108 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
109 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
110 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
111 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
112 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
113 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
114 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
115 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
116 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
117 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
118 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
119 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
120 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
121 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
122 #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
123 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
124 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
125 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
126 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
127 #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
128 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
129 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
130 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
131 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
143 #define CREP (1 << 7)
144 #define BL(x) (((x) & 0x7) << 8)
146 #define BCD(x) (((x) & 0x3) << 12)
147 #define BCS(x) (((x) & 0x3) << 14)
148 #define DSZ(x) (((x) & 0x7) << 16)
150 #define CSREC(x) (((x) & 0x7) << 20)
151 #define AUS (1 << 23)
152 #define GBC(x) (((x) & 0x7) << 24)
154 #define PSZ(x) (((x) & 0x0f << 28)
159 #define ADH(x) (((x) & 0x3))
160 #define DAPS(x) (((x) & 0x0f << 4)
163 #define MUX16_BYP (1 << 12)
168 #define RCSN(x) (((x) & 0x7))
169 #define RCSA(x) (((x) & 0x7) << 4)
170 #define OEN(x) (((x) & 0x7) << 8)
171 #define OEA(x) (((x) & 0x7) << 12)
172 #define RADVN(x) (((x) & 0x7) << 16)
173 #define RAL (1 << 19)
174 #define RADVA(x) (((x) & 0x7) << 20)
175 #define RWSC(x) (((x) & 0x3f) << 24)
180 #define RBEN(x) (((x) & 0x7))
182 #define RBEA(x) (((x) & 0x7) << 4)
183 #define RL(x) (((x) & 0x3) << 8)
184 #define PAT(x) (((x) & 0x7) << 12)
185 #define APR (1 << 15)
190 #define WCSN(x) (((x) & 0x7))
191 #define WCSA(x) (((x) & 0x7) << 3)
192 #define WEN(x) (((x) & 0x7) << 6)
193 #define WEA(x) (((x) & 0x7) << 9)
194 #define WBEN(x) (((x) & 0x7) << 12)
195 #define WBEA(x) (((x) & 0x7) << 15)
196 #define WADVN(x) (((x) & 0x7) << 18)
197 #define WADVA(x) (((x) & 0x7) << 21)
198 #define WWSC(x) (((x) & 0x3f) << 24)
199 #define WBED1 (1 << 30)
200 #define WAL (1 << 31)
211 #define GBCD(x) (((x) & 0x3) << 1)
212 #define INTEN (1 << 4)
213 #define INTPOL (1 << 5)
214 #define WDOG_EN (1 << 8)
215 #define WDOG_LIMIT(x) (((x) & 0x3) << 9)
218 #define CS0_64M_CS1_64M 1
219 #define CS0_64M_CS1_32M_CS2_32M 2
220 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
223 * Number of GPIO pins per port
225 #define GPIO_NUM_PIN 32
227 #define IIM_SREV 0x24
228 #define ROM_SI_REV 0x48
230 #define NFC_BUF_SIZE 0x1000
233 #define M4IF_FBPM0 0x40
234 #define M4IF_FIDBP 0x48
236 /* Assuming 24MHz input clock with doubler ON */
238 #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
239 #define DP_MFD_864 (180 - 1) /* PL Dither mode */
240 #define DP_MFN_864 180
241 #define DP_MFN_800_DIT 60 /* PL Dither mode */
243 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
244 #define DP_MFD_850 (48 - 1)
245 #define DP_MFN_850 41
247 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
248 #define DP_MFD_800 (3 - 1)
251 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
252 #define DP_MFD_700 (24 - 1)
255 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
256 #define DP_MFD_665 (96 - 1)
257 #define DP_MFN_665 89
259 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
260 #define DP_MFD_532 (24 - 1)
261 #define DP_MFN_532 13
263 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
264 #define DP_MFD_400 (3 - 1)
267 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
268 #define DP_MFD_216 (4 - 1)
271 #define CHIP_REV_1_0 0x10
272 #define CHIP_REV_1_1 0x11
273 #define CHIP_REV_2_0 0x20
274 #define CHIP_REV_2_5 0x25
275 #define CHIP_REV_3_0 0x30
277 #define BOARD_REV_1_0 0x0
278 #define BOARD_REV_2_0 0x1
280 #define IMX_IIM_BASE (IIM_BASE_ADDR)
282 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
283 #include <asm/types.h>
285 extern void imx_get_mac_from_fuse(unsigned char *mac);
287 #define __REG(x) (*((volatile u32 *)(x)))
288 #define __REG16(x) (*((volatile u16 *)(x)))
289 #define __REG8(x) (*((volatile u8 *)(x)))
325 #if defined(CONFIG_MX53)
389 #if defined(CONFIG_MX51)
399 #elif defined(CONFIG_MX53)
412 /* System Reset Controller (SRC) */
457 struct fuse_bank1_regs {
463 #endif /* __ASSEMBLER__*/
465 #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */