2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
24 #define __ASM_ARCH_MX5_IMX_REGS_H__
28 #if defined(CONFIG_MX51)
29 #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
30 #define IPU_SOC_BASE_ADDR 0x40000000
31 #define IPU_SOC_OFFSET 0x1E000000
32 #define SPBA0_BASE_ADDR 0x70000000
33 #define AIPS1_BASE_ADDR 0x73F00000
34 #define AIPS2_BASE_ADDR 0x83F00000
35 #define CSD0_BASE_ADDR 0x90000000
36 #define CSD1_BASE_ADDR 0xA0000000
37 #define NFC_BASE_ADDR_AXI 0xCFFF0000
38 #define CS1_BASE_ADDR 0xB8000000
39 #elif defined(CONFIG_MX53)
40 #define IPU_SOC_BASE_ADDR 0x18000000
41 #define IPU_SOC_OFFSET 0x06000000
42 #define SPBA0_BASE_ADDR 0x50000000
43 #define AIPS1_BASE_ADDR 0x53F00000
44 #define AIPS2_BASE_ADDR 0x63F00000
45 #define CSD0_BASE_ADDR 0x70000000
46 #define CSD1_BASE_ADDR 0xB0000000
47 #define NFC_BASE_ADDR_AXI 0xF7FF0000
48 #define IRAM_BASE_ADDR 0xF8000000
49 #define CS1_BASE_ADDR 0xF4000000
50 #define SATA_BASE_ADDR 0x10000000
52 #error "CPU_TYPE not defined"
55 #define IRAM_SIZE 0x00020000 /* 128 KB */
58 * SPBA global module enabled #0
60 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
61 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
62 #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000)
63 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
64 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
65 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
66 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
67 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
68 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
69 #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
70 #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
71 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
76 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
77 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
78 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
79 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
80 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
81 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
82 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
83 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
84 #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
85 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
86 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
87 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
88 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
89 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
90 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
91 #define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000)
92 #define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000)
93 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
94 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
95 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
97 #if defined(CONFIG_MX53)
98 #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
99 #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
100 #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
101 #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
102 #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
107 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
108 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
109 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
111 #define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000)
113 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
114 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
115 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
116 #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
117 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
118 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
119 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
120 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
121 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
122 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
123 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
124 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
125 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
126 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
127 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
128 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
129 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
130 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
131 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
132 #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
133 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
134 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
135 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
136 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
137 #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
138 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
139 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
140 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
141 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
143 #if defined(CONFIG_MX53)
144 #define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
157 #define CREP (1 << 7)
158 #define BL(x) (((x) & 0x7) << 8)
160 #define BCD(x) (((x) & 0x3) << 12)
161 #define BCS(x) (((x) & 0x3) << 14)
162 #define DSZ(x) (((x) & 0x7) << 16)
164 #define CSREC(x) (((x) & 0x7) << 20)
165 #define AUS (1 << 23)
166 #define GBC(x) (((x) & 0x7) << 24)
168 #define PSZ(x) (((x) & 0x0f << 28)
173 #define ADH(x) (((x) & 0x3))
174 #define DAPS(x) (((x) & 0x0f << 4)
177 #define MUX16_BYP (1 << 12)
182 #define RCSN(x) (((x) & 0x7))
183 #define RCSA(x) (((x) & 0x7) << 4)
184 #define OEN(x) (((x) & 0x7) << 8)
185 #define OEA(x) (((x) & 0x7) << 12)
186 #define RADVN(x) (((x) & 0x7) << 16)
187 #define RAL (1 << 19)
188 #define RADVA(x) (((x) & 0x7) << 20)
189 #define RWSC(x) (((x) & 0x3f) << 24)
194 #define RBEN(x) (((x) & 0x7))
196 #define RBEA(x) (((x) & 0x7) << 4)
197 #define RL(x) (((x) & 0x3) << 8)
198 #define PAT(x) (((x) & 0x7) << 12)
199 #define APR (1 << 15)
204 #define WCSN(x) (((x) & 0x7))
205 #define WCSA(x) (((x) & 0x7) << 3)
206 #define WEN(x) (((x) & 0x7) << 6)
207 #define WEA(x) (((x) & 0x7) << 9)
208 #define WBEN(x) (((x) & 0x7) << 12)
209 #define WBEA(x) (((x) & 0x7) << 15)
210 #define WADVN(x) (((x) & 0x7) << 18)
211 #define WADVA(x) (((x) & 0x7) << 21)
212 #define WWSC(x) (((x) & 0x3f) << 24)
213 #define WBED1 (1 << 30)
214 #define WAL (1 << 31)
222 #define CS0_64M_CS1_64M 1
223 #define CS0_64M_CS1_32M_CS2_32M 2
224 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
227 * CSPI register definitions
230 #define MXC_CSPICTRL_EN (1 << 0)
231 #define MXC_CSPICTRL_MODE (1 << 1)
232 #define MXC_CSPICTRL_XCH (1 << 2)
233 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
234 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
235 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
236 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
237 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
238 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
239 #define MXC_CSPICTRL_MAXBITS 0xfff
240 #define MXC_CSPICTRL_TC (1 << 7)
241 #define MXC_CSPICTRL_RXOVF (1 << 6)
242 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
243 #define MAX_SPI_BYTES 32
245 /* Bit position inside CTRL register to be associated with SS */
246 #define MXC_CSPICTRL_CHAN 18
248 /* Bit position inside CON register to be associated with SS */
249 #define MXC_CSPICON_POL 4
250 #define MXC_CSPICON_PHA 0
251 #define MXC_CSPICON_SSPOL 12
252 #define MXC_SPI_BASE_ADDRESSES \
258 * Number of GPIO pins per port
260 #define GPIO_NUM_PIN 32
262 #define IIM_SREV 0x24
263 #define ROM_SI_REV 0x48
265 #define NFC_BUF_SIZE 0x1000
268 #define M4IF_FBPM0 0x40
269 #define M4IF_FIDBP 0x48
270 #define M4IF_GENP_WEIM_MM_MASK 0x00000001
271 #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
273 /* Assuming 24MHz input clock with doubler ON */
275 #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
276 #define DP_MFD_864 (180 - 1) /* PL Dither mode */
277 #define DP_MFN_864 180
278 #define DP_MFN_800_DIT 60 /* PL Dither mode */
280 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
281 #define DP_MFD_850 (48 - 1)
282 #define DP_MFN_850 41
284 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
285 #define DP_MFD_800 (3 - 1)
288 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
289 #define DP_MFD_700 (24 - 1)
292 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
293 #define DP_MFD_665 (96 - 1)
294 #define DP_MFN_665 89
296 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
297 #define DP_MFD_532 (24 - 1)
298 #define DP_MFN_532 13
300 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
301 #define DP_MFD_400 (3 - 1)
304 #define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
305 #define DP_MFD_455 (48 - 1)
306 #define DP_MFN_455 23
308 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
309 #define DP_MFD_216 (4 - 1)
312 #define CHIP_REV_1_0 0x10
313 #define CHIP_REV_1_1 0x11
314 #define CHIP_REV_2_0 0x20
315 #define CHIP_REV_2_5 0x25
316 #define CHIP_REV_3_0 0x30
318 #define BOARD_REV_1_0 0x0
319 #define BOARD_REV_2_0 0x1
321 #define BOARD_VER_OFFSET 0x8
323 #define IMX_IIM_BASE (IIM_BASE_ADDR)
325 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
326 #include <asm/types.h>
328 #define __REG(x) (*((volatile u32 *)(x)))
329 #define __REG16(x) (*((volatile u16 *)(x)))
330 #define __REG8(x) (*((volatile u8 *)(x)))
366 #if defined(CONFIG_MX53)
430 #if defined(CONFIG_MX51)
440 #elif defined(CONFIG_MX53)
453 /* System Reset Controller (SRC) */
464 u32 lpscmr; /* 0x00 */
465 u32 lpsclr; /* 0x04 */
466 u32 lpsar; /* 0x08 */
467 u32 lpsmcr; /* 0x0c */
470 u32 lppdr; /* 0x18 */
472 u32 hpcmr; /* 0x20 */
473 u32 hpclr; /* 0x24 */
474 u32 hpamr; /* 0x28 */
475 u32 hpalr; /* 0x2c */
477 u32 hpisr; /* 0x34 */
478 u32 hpienr; /* 0x38 */
513 #if defined(CONFIG_MX51)
515 #elif defined(CONFIG_MX53)
520 struct fuse_bank0_regs {
525 struct fuse_bank1_regs {
531 #endif /* __ASSEMBLER__*/
533 #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */