2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
10 #define CCM_CCOSR 0x020c4060
11 #define CCM_CCGR0 0x020C4068
12 #define CCM_CCGR1 0x020C406c
13 #define CCM_CCGR2 0x020C4070
14 #define CCM_CCGR3 0x020C4074
15 #define CCM_CCGR4 0x020C4078
16 #define CCM_CCGR5 0x020C407c
17 #define CCM_CCGR6 0x020C4080
19 #define PMU_MISC2 0x020C8170
27 u32 cacrr; /* 0x0010*/
31 u32 cscmr2; /* 0x0020 */
35 u32 cdcdr; /* 0x0030 */
39 u32 cscdr4; /* 0x0040 */
43 u32 ctor; /* 0x0050 */
47 u32 ccosr; /* 0x0060 */
51 u32 CCGR2; /* 0x0070 */
55 u32 CCGR6; /* 0x0080 */
59 u32 analog_pll_sys; /* 0x4000 */
60 u32 analog_pll_sys_set;
61 u32 analog_pll_sys_clr;
62 u32 analog_pll_sys_tog;
63 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
64 u32 analog_usb1_pll_480_ctrl_set;
65 u32 analog_usb1_pll_480_ctrl_clr;
66 u32 analog_usb1_pll_480_ctrl_tog;
67 u32 analog_reserved0[4];
68 u32 analog_pll_528; /* 0x4030 */
69 u32 analog_pll_528_set;
70 u32 analog_pll_528_clr;
71 u32 analog_pll_528_tog;
72 u32 analog_pll_528_ss; /* 0x4040 */
73 u32 analog_reserved1[3];
74 u32 analog_pll_528_num; /* 0x4050 */
75 u32 analog_reserved2[3];
76 u32 analog_pll_528_denom; /* 0x4060 */
77 u32 analog_reserved3[3];
78 u32 analog_pll_audio; /* 0x4070 */
79 u32 analog_pll_audio_set;
80 u32 analog_pll_audio_clr;
81 u32 analog_pll_audio_tog;
82 u32 analog_pll_audio_num; /* 0x4080*/
83 u32 analog_reserved4[3];
84 u32 analog_pll_audio_denom; /* 0x4090 */
85 u32 analog_reserved5[3];
86 u32 analog_pll_video; /* 0x40a0 */
87 u32 analog_pll_video_set;
88 u32 analog_pll_video_clr;
89 u32 analog_pll_video_tog;
90 u32 analog_pll_video_num; /* 0x40b0 */
91 u32 analog_reserved6[3];
92 u32 analog_pll_video_denom; /* 0x40c0 */
93 u32 analog_reserved7[7];
94 u32 analog_pll_enet; /* 0x40e0 */
95 u32 analog_pll_enet_set;
96 u32 analog_pll_enet_clr;
97 u32 analog_pll_enet_tog;
98 u32 analog_pfd_480; /* 0x40f0 */
99 u32 analog_pfd_480_set;
100 u32 analog_pfd_480_clr;
101 u32 analog_pfd_480_tog;
102 u32 analog_pfd_528; /* 0x4100 */
103 u32 analog_pfd_528_set;
104 u32 analog_pfd_528_clr;
105 u32 analog_pfd_528_tog;
106 /* PMU Memory Map/Register Definition */
120 u32 pmu_reg_core_set;
121 u32 pmu_reg_core_clr;
122 u32 pmu_reg_core_tog;
135 /* TEMPMON Memory Map/Register Definition */
144 /* USB Analog Memory Map/Register Definition */
145 u32 usb1_vbus_detect;
146 u32 usb1_vbus_detect_set;
147 u32 usb1_vbus_detect_clr;
148 u32 usb1_vbus_detect_tog;
149 u32 usb1_chrg_detect;
150 u32 usb1_chrg_detect_set;
151 u32 usb1_chrg_detect_clr;
152 u32 usb1_chrg_detect_tog;
153 u32 usb1_vbus_det_stat;
154 u32 usb1_vbus_det_stat_set;
155 u32 usb1_vbus_det_stat_clr;
156 u32 usb1_vbus_det_stat_tog;
157 u32 usb1_chrg_det_stat;
158 u32 usb1_chrg_det_stat_set;
159 u32 usb1_chrg_det_stat_clr;
160 u32 usb1_chrg_det_stat_tog;
162 u32 usb1_loopback_set;
163 u32 usb1_loopback_clr;
164 u32 usb1_loopback_tog;
169 u32 usb2_vbus_detect;
170 u32 usb2_vbus_detect_set;
171 u32 usb2_vbus_detect_clr;
172 u32 usb2_vbus_detect_tog;
173 u32 usb2_chrg_detect;
174 u32 usb2_chrg_detect_set;
175 u32 usb2_chrg_detect_clr;
176 u32 usb2_chrg_detect_tog;
177 u32 usb2_vbus_det_stat;
178 u32 usb2_vbus_det_stat_set;
179 u32 usb2_vbus_det_stat_clr;
180 u32 usb2_vbus_det_stat_tog;
181 u32 usb2_chrg_det_stat;
182 u32 usb2_chrg_det_stat_set;
183 u32 usb2_chrg_det_stat_clr;
184 u32 usb2_chrg_det_stat_tog;
186 u32 usb2_loopback_set;
187 u32 usb2_loopback_clr;
188 u32 usb2_loopback_tog;
195 /* For i.MX 6SoloLite */
196 u32 digprog_sololite;
200 /* Define the bits in register CCR */
201 #define MXC_CCM_CCR_RBC_EN (1 << 27)
202 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
203 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
204 /* CCR_WB does not exist on i.MX6SX/UL */
205 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
206 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
207 #define MXC_CCM_CCR_COSC_EN (1 << 12)
209 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
211 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
213 #define MXC_CCM_CCR_OSCNT_OFFSET 0
215 /* Define the bits in register CCDR */
216 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
217 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
218 /* Exists on i.MX6QP */
219 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
221 /* Define the bits in register CSR */
222 #define MXC_CCM_CSR_COSC_READY (1 << 5)
223 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
225 /* Define the bits in register CCSR */
226 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
227 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
228 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
229 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
230 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
231 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
232 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
233 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
234 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
235 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
236 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
238 /* Define the bits in register CACRR */
239 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
240 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
242 /* Define the bits in register CBCDR */
243 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
244 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
245 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26)
246 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
247 /* MMDC_CH0 not exists on i.MX6SX */
248 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
249 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
250 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
251 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
252 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
253 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
254 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
255 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
256 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
257 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
258 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
259 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
260 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
261 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
263 /* Define the bits in register CBCMR */
264 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
265 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
266 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
267 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
268 /* LCDIF on i.MX6SX/UL */
269 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23)
270 #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23
271 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
272 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
273 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
274 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
275 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
276 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
277 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
279 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
280 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
281 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
282 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
284 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
285 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
287 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
289 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
290 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
291 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
292 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
293 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
294 /* Exists on i.MX6QP */
295 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
297 /* Define the bits in register CSCMR1 */
298 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
299 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
300 /* QSPI1 exist on i.MX6SX/UL */
301 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
302 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
303 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
304 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
305 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
306 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
307 /* LCFIF2_PODF on i.MX6SX */
308 #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20)
309 #define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20
310 /* ACLK_EMI on i.MX6DQ/SDL/DQP */
311 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
312 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
313 /* CSCMR1_GPMI/BCH exist on i.MX6UL */
314 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
315 #define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18)
316 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
317 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
318 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
319 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
320 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
321 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
322 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
323 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
324 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
325 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
326 /* QSPI1 exist on i.MX6SX/UL */
327 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
328 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
329 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
330 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
331 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
333 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
335 /* Define the bits in register CSCMR2 */
337 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
338 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
340 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
341 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
342 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
343 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
344 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
345 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
346 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
348 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
349 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
351 /* Define the bits in register CSCDR1 */
353 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
354 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
356 /* CSCDR1_GPMI/BCH exist on i.MX6UL */
357 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22)
358 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
359 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19)
360 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
362 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
363 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
364 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
365 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
366 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
367 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
368 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
369 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
371 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
372 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
373 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
374 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
376 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
377 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
378 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
379 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
381 /* Define the bits in register CS1CDR */
383 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22)
384 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22
385 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16)
386 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16
387 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6)
388 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6
389 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F
390 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0
392 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
393 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
394 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
395 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
396 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
397 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
398 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
399 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
400 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
401 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
402 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
403 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
405 /* Define the bits in register CS2CDR */
406 /* QSPI2 on i.MX6SX */
407 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
408 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
409 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
410 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
412 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
413 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
414 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
415 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
417 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
418 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
419 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
420 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
421 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
422 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
424 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
425 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
426 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
427 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
428 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16
429 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
431 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
432 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
433 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
434 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
435 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
436 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
437 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
438 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
439 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
440 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
441 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
442 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
444 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
445 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
446 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
447 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
448 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
449 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
450 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
451 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
453 /* Define the bits in register CDCDR */
455 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
456 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
457 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
459 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
460 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
461 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22)
462 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
463 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
464 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
465 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
466 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
467 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
468 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
469 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
470 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
472 /* Define the bits in register CHSCCDR */
474 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
475 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
476 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
477 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
478 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
479 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
480 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
481 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
482 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
483 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
484 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
485 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
487 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
488 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
489 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
490 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
491 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
492 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
493 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
494 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
495 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
496 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
497 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
498 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
501 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15)
502 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15
503 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12)
504 #define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12
505 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9)
506 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9
508 #define CHSCCDR_CLK_SEL_LDB_DI0 3
509 #define CHSCCDR_PODF_DIVIDE_BY_3 2
510 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
512 /* Define the bits in register CSCDR2 */
513 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
514 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
515 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
516 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
517 /* LCDIF1 on i.MX6SX/UL */
518 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15)
519 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15
520 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12)
521 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12
522 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9)
523 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9
524 /* LCDIF2 on i.MX6SX */
525 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6)
526 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6
527 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3)
528 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3
529 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0)
530 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0
532 /* All IPU2_DI1 are LCDIF1 on MX6SX */
533 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
534 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
535 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
536 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
537 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
538 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
539 /* All IPU2_DI0 are LCDIF2 on MX6SX */
540 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
541 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
542 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
543 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
544 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
545 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
547 /* Define the bits in register CSCDR3 */
548 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
549 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
550 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
551 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
552 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
553 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
554 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
555 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
557 /* Define the bits in register CDHIPR */
558 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
559 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
561 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
563 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
564 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
565 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
566 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
568 /* Define the bits in register CLPCR */
569 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
570 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
572 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
573 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
574 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
576 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
577 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
579 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
580 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
582 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
583 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
584 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
585 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
586 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
587 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
588 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
589 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
591 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
592 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
593 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
595 #define MXC_CCM_CLPCR_LPM_MASK 0x3
596 #define MXC_CCM_CLPCR_LPM_OFFSET 0
598 /* Define the bits in register CISR */
599 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
601 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
603 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
604 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
605 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
606 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
607 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
608 #define MXC_CCM_CISR_COSC_READY (1 << 6)
609 #define MXC_CCM_CISR_LRF_PLL 1
611 /* Define the bits in register CIMR */
612 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
614 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
616 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
617 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
618 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
619 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
620 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
621 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
622 #define MXC_CCM_CIMR_MASK_LRF_PLL 1
624 /* Define the bits in register CCOSR */
625 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
626 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
627 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
628 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
629 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
630 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
631 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
632 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
633 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
634 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
635 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
637 /* Define the bits in registers CGPR */
638 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
639 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
640 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
641 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
643 /* Define the bits in registers CCGRx */
644 #define MXC_CCM_CCGR_CG_MASK 3
647 #define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10
648 #define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET)
649 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12
650 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET)
652 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
653 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
654 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
655 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
656 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
657 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
658 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
659 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
660 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
661 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
662 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
663 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
664 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
665 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
666 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
667 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
668 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
669 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
670 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
671 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
672 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
673 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
674 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
675 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
676 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
677 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
678 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
679 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
681 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
682 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
684 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
685 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
688 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
689 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
690 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
691 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
692 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
693 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
694 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
695 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
696 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
697 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
698 /* CCGR1_ENET does not exist on i.MX6SX/UL */
699 #define MXC_CCM_CCGR1_ENET_OFFSET 10
700 #define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET)
701 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
702 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
703 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
704 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
705 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
706 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
708 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
709 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
711 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
712 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
713 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
714 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
716 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
717 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
719 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
720 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
722 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
723 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
724 #define MXC_CCM_CCGR1_CANFD_OFFSET 30
725 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
728 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
729 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
731 #define MXC_CCM_CCGR2_CSI_OFFSET 2
732 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
735 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
736 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
738 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
739 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
740 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
741 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
742 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
743 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
744 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
745 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
746 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
747 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
748 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
749 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
750 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
751 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
752 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
753 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
754 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
755 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
756 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
757 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
758 /* i.MX6SX/UL LCD and PXP */
759 #define MXC_CCM_CCGR2_LCD_OFFSET 28
760 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
761 #define MXC_CCM_CCGR2_PXP_OFFSET 30
762 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
764 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
765 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
766 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
767 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
770 #define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0
771 #define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET)
772 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4
773 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET)
775 /* Exist on i.MX6SX */
776 #define MXC_CCM_CCGR3_M4_OFFSET 2
777 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
779 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4
780 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET)
781 #define MXC_CCM_CCGR3_ENET_OFFSET 4
782 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
783 #define MXC_CCM_CCGR3_QSPI_OFFSET 14
784 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
786 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
787 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
788 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
789 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
790 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
791 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
793 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
794 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
795 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
796 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
797 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
798 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
799 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
800 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
802 /* QSPI1 exists on i.MX6SX/UL */
803 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
804 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
806 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
807 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
808 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
809 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
811 /* A7_CLKDIV/WDOG1 on i.MX6UL */
812 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16
813 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
814 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18
815 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
817 #define MXC_CCM_CCGR3_MLB_OFFSET 18
818 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
819 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
820 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
822 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
823 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
825 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
826 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
827 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
828 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
830 #define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6
831 #define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET)
832 #define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8
833 #define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET)
834 #define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10
835 #define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET)
837 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
838 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
839 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
840 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
842 /* GPIO4 on i.MX6UL/ULL */
843 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
844 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
847 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
848 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
852 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30
853 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET)
855 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
856 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
857 /* QSPI2 on i.MX6SX */
858 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
859 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
860 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
861 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
862 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
863 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
864 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
865 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
866 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
867 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
868 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
869 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
870 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
871 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
872 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
873 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
874 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
875 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
876 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
877 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
878 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
879 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
880 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
881 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
883 #define MXC_CCM_CCGR5_ROM_OFFSET 0
884 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
886 #define MXC_CCM_CCGR5_SATA_OFFSET 4
887 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
889 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
890 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
891 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
892 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
893 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
894 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
895 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
896 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
897 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
898 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
899 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
900 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
901 #define MXC_CCM_CCGR5_UART_OFFSET 24
902 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
903 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
904 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
906 #define MXC_CCM_CCGR5_SAI1_OFFSET 20
907 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
908 #define MXC_CCM_CCGR5_SAI2_OFFSET 30
909 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
912 /* PRG_CLK0 exists on i.MX6QP */
913 #define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24)
915 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
916 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
917 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
918 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
919 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
920 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
921 #define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6
922 #define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET)
923 #define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8
924 #define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET)
926 #define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8
927 #define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET)
928 /* GPMI/BCH on i.MX6UL */
929 #define MXC_CCM_CCGR6_BCH_OFFSET 6
930 #define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
931 #define MXC_CCM_CCGR6_GPMI_OFFSET 8
932 #define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
934 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
935 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
936 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
937 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
938 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
939 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
941 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18
942 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET)
943 /* The following *CCGR6* exist only i.MX6SX */
944 #define MXC_CCM_CCGR6_PWM8_OFFSET 16
945 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
946 #define MXC_CCM_CCGR6_VADC_OFFSET 20
947 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
948 #define MXC_CCM_CCGR6_GIS_OFFSET 22
949 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
950 #define MXC_CCM_CCGR6_I2C4_OFFSET 24
951 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
952 #define MXC_CCM_CCGR6_PWM5_OFFSET 26
953 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
954 #define MXC_CCM_CCGR6_PWM6_OFFSET 28
955 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
956 #define MXC_CCM_CCGR6_PWM7_OFFSET 30
957 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
958 /* The two does not exist on i.MX6SX */
959 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
960 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
962 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
963 #define BP_ANADIG_PLL_SYS_RSVD0 20
964 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
965 #define BF_ANADIG_PLL_SYS_RSVD0(v) \
966 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
967 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
968 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
969 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
970 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
971 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
972 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
973 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
974 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
975 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
976 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
977 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
978 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
979 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
980 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
981 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
982 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
983 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
984 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
985 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
986 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
987 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
988 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
989 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
991 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
992 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
993 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
994 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
995 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
996 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
997 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
998 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
999 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
1000 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
1001 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
1002 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
1003 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
1004 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
1005 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
1006 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
1007 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
1008 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
1009 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
1010 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
1011 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
1012 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
1013 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
1014 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
1015 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
1016 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
1017 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
1018 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
1019 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
1020 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
1021 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
1023 #define BM_ANADIG_PLL_528_LOCK 0x80000000
1024 #define BP_ANADIG_PLL_528_RSVD1 19
1025 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
1026 #define BF_ANADIG_PLL_528_RSVD1(v) \
1027 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
1028 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
1029 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
1030 #define BM_ANADIG_PLL_528_BYPASS 0x00010000
1031 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
1032 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
1033 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
1034 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
1035 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
1036 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
1037 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
1038 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
1039 #define BM_ANADIG_PLL_528_ENABLE 0x00002000
1040 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
1041 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
1042 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
1043 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200
1044 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
1045 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080
1046 #define BP_ANADIG_PLL_528_RSVD0 1
1047 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E
1048 #define BF_ANADIG_PLL_528_RSVD0(v) \
1049 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
1050 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
1052 #define BP_ANADIG_PLL_528_SS_STOP 16
1053 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
1054 #define BF_ANADIG_PLL_528_SS_STOP(v) \
1055 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
1056 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
1057 #define BP_ANADIG_PLL_528_SS_STEP 0
1058 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
1059 #define BF_ANADIG_PLL_528_SS_STEP(v) \
1060 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
1062 #define BP_ANADIG_PLL_528_NUM_RSVD0 30
1063 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
1064 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
1065 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
1066 #define BP_ANADIG_PLL_528_NUM_A 0
1067 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
1068 #define BF_ANADIG_PLL_528_NUM_A(v) \
1069 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
1071 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30
1072 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
1073 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
1074 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
1075 #define BP_ANADIG_PLL_528_DENOM_B 0
1076 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
1077 #define BF_ANADIG_PLL_528_DENOM_B(v) \
1078 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
1080 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
1081 #define BP_ANADIG_PLL_AUDIO_RSVD0 22
1082 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
1083 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
1084 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
1085 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
1086 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
1087 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
1088 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
1089 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1090 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
1091 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
1092 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
1093 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
1094 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
1095 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
1096 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1097 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
1098 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
1099 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
1100 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
1101 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
1102 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
1103 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
1104 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
1105 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
1106 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
1107 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
1108 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
1109 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
1110 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
1111 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
1113 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
1114 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
1115 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
1116 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
1117 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
1118 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
1119 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
1120 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
1122 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
1123 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
1124 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
1125 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
1126 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
1127 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
1128 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
1129 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
1131 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
1132 #define BP_ANADIG_PLL_VIDEO_RSVD0 22
1133 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
1134 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
1135 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
1136 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
1137 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
1138 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
1139 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
1140 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
1141 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
1142 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
1143 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
1144 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
1145 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
1146 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
1147 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1148 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
1149 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
1150 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
1151 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
1152 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
1153 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
1154 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
1155 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
1156 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
1157 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
1158 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
1159 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
1160 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
1161 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
1162 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
1164 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
1165 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
1166 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
1167 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
1168 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
1169 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
1170 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
1171 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
1173 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
1174 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
1175 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
1176 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
1177 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
1178 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
1179 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
1180 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
1182 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000
1183 #define BP_ANADIG_PLL_ENET_RSVD1 21
1184 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
1185 #define BF_ANADIG_PLL_ENET_RSVD1(v) \
1186 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
1187 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
1188 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
1189 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
1190 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
1191 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
1192 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
1193 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
1194 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
1195 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
1196 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1197 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
1198 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
1199 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
1200 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
1201 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
1202 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
1203 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
1204 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
1205 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
1206 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
1207 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
1208 #define BP_ANADIG_PLL_ENET_RSVD0 2
1209 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
1210 #define BF_ANADIG_PLL_ENET_RSVD0(v) \
1211 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
1212 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1213 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
1214 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
1215 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
1217 /* ENET2 for i.MX6SX/UL */
1218 #define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
1219 #define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
1220 #define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \
1221 (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
1223 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
1224 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
1225 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
1226 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
1227 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1228 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
1229 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
1230 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
1231 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
1232 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
1233 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1234 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
1235 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
1236 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
1237 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
1238 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
1239 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1240 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
1241 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
1242 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
1243 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
1244 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
1245 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1246 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1248 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
1249 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
1250 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
1251 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
1252 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1253 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1254 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
1255 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
1256 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
1257 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
1258 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1259 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1260 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
1261 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
1262 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
1263 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
1264 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1265 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1266 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
1267 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
1268 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1269 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
1270 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1271 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1273 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
1274 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
1275 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4
1277 #define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
1278 #define BP_PMU_MISC2_AUDIO_DIV_MSB 23
1280 #define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15)
1281 #define BP_PMU_MISC2_AUDIO_DIV_LSB 15
1283 #define PMU_MISC2_AUDIO_DIV(v) \
1284 (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \
1285 (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \
1286 ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \
1287 BP_PMU_MISC2_AUDIO_DIV_LSB))
1289 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */