2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
13 #define CONFIG_SYS_CACHELINE_SIZE 64
15 #define CONFIG_SYS_CACHELINE_SIZE 32
18 #define ROMCP_ARB_BASE_ADDR 0x00000000
19 #define ROMCP_ARB_END_ADDR 0x000FFFFF
22 #define GPU_2D_ARB_BASE_ADDR 0x02200000
23 #define GPU_2D_ARB_END_ADDR 0x02203FFF
24 #define OPENVG_ARB_BASE_ADDR 0x02204000
25 #define OPENVG_ARB_END_ADDR 0x02207FFF
26 #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
27 #define CAAM_ARB_BASE_ADDR 0x00100000
28 #define CAAM_ARB_END_ADDR 0x00107FFF
29 #define GPU_ARB_BASE_ADDR 0x01800000
30 #define GPU_ARB_END_ADDR 0x01803FFF
31 #define APBH_DMA_ARB_BASE_ADDR 0x01804000
32 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
33 #define M4_BOOTROM_BASE_ADDR 0x007F8000
36 #define CAAM_ARB_BASE_ADDR 0x00100000
37 #define CAAM_ARB_END_ADDR 0x00103FFF
38 #define APBH_DMA_ARB_BASE_ADDR 0x00110000
39 #define APBH_DMA_ARB_END_ADDR 0x00117FFF
40 #define HDMI_ARB_BASE_ADDR 0x00120000
41 #define HDMI_ARB_END_ADDR 0x00128FFF
42 #define GPU_3D_ARB_BASE_ADDR 0x00130000
43 #define GPU_3D_ARB_END_ADDR 0x00133FFF
44 #define GPU_2D_ARB_BASE_ADDR 0x00134000
45 #define GPU_2D_ARB_END_ADDR 0x00137FFF
46 #define DTCP_ARB_BASE_ADDR 0x00138000
47 #define DTCP_ARB_END_ADDR 0x0013BFFF
48 #endif /* CONFIG_MX6SL */
50 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
51 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
52 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
54 /* GPV - PL301 configuration ports */
55 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
56 #define GPV2_BASE_ADDR 0x00D00000
58 #define GPV2_BASE_ADDR 0x00200000
61 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
62 #define GPV3_BASE_ADDR 0x00E00000
63 #define GPV4_BASE_ADDR 0x00F00000
64 #define GPV5_BASE_ADDR 0x01000000
65 #define GPV6_BASE_ADDR 0x01100000
66 #define PCIE_ARB_BASE_ADDR 0x08000000
67 #define PCIE_ARB_END_ADDR 0x08FFFFFF
70 #define GPV3_BASE_ADDR 0x00300000
71 #define GPV4_BASE_ADDR 0x00800000
72 #define PCIE_ARB_BASE_ADDR 0x01000000
73 #define PCIE_ARB_END_ADDR 0x01FFFFFF
76 #define IRAM_BASE_ADDR 0x00900000
77 #define SCU_BASE_ADDR 0x00A00000
78 #define IC_INTERFACES_BASE_ADDR 0x00A00100
79 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
80 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
81 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
82 #define L2_PL310_BASE 0x00A02000
83 #define GPV0_BASE_ADDR 0x00B00000
84 #define GPV1_BASE_ADDR 0x00C00000
86 #define AIPS1_ARB_BASE_ADDR 0x02000000
87 #define AIPS1_ARB_END_ADDR 0x020FFFFF
88 #define AIPS2_ARB_BASE_ADDR 0x02100000
89 #define AIPS2_ARB_END_ADDR 0x021FFFFF
90 /* AIPS3 only on i.MX6SX */
91 #define AIPS3_ARB_BASE_ADDR 0x02200000
92 #define AIPS3_ARB_END_ADDR 0x022FFFFF
94 #define WEIM_ARB_BASE_ADDR 0x50000000
95 #define WEIM_ARB_END_ADDR 0x57FFFFFF
96 #define QSPI0_AMBA_BASE 0x60000000
97 #define QSPI0_AMBA_END 0x6FFFFFFF
98 #define QSPI1_AMBA_BASE 0x70000000
99 #define QSPI1_AMBA_END 0x7FFFFFFF
100 #elif defined(CONFIG_MX6UL)
101 #define WEIM_ARB_BASE_ADDR 0x50000000
102 #define WEIM_ARB_END_ADDR 0x57FFFFFF
103 #define QSPI0_AMBA_BASE 0x60000000
104 #define QSPI0_AMBA_END 0x6FFFFFFF
106 #define SATA_ARB_BASE_ADDR 0x02200000
107 #define SATA_ARB_END_ADDR 0x02203FFF
108 #define OPENVG_ARB_BASE_ADDR 0x02204000
109 #define OPENVG_ARB_END_ADDR 0x02207FFF
110 #define HSI_ARB_BASE_ADDR 0x02208000
111 #define HSI_ARB_END_ADDR 0x0220BFFF
112 #define IPU1_ARB_BASE_ADDR 0x02400000
113 #define IPU1_ARB_END_ADDR 0x027FFFFF
114 #define IPU2_ARB_BASE_ADDR 0x02800000
115 #define IPU2_ARB_END_ADDR 0x02BFFFFF
116 #define WEIM_ARB_BASE_ADDR 0x08000000
117 #define WEIM_ARB_END_ADDR 0x0FFFFFFF
120 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
121 #define MMDC0_ARB_BASE_ADDR 0x80000000
122 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
123 #define MMDC1_ARB_BASE_ADDR 0xC0000000
124 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
126 #define MMDC0_ARB_BASE_ADDR 0x10000000
127 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
128 #define MMDC1_ARB_BASE_ADDR 0x80000000
129 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
133 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
134 #define IPU_SOC_OFFSET 0x00200000
137 /* Defines for Blocks connected via AIPS (SkyBlue) */
138 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
139 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
140 #define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
141 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
142 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
143 #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
145 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
146 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
147 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
148 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
149 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
151 #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
152 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
153 #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
154 #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
155 #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
156 #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
157 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
158 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
161 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
163 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
164 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
165 #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
166 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
167 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
168 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
169 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
173 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
174 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
176 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
178 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
179 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
180 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
181 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
182 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
183 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
184 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
185 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
186 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
187 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
188 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
189 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
190 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
191 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
192 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
193 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
194 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
195 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
196 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
197 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
198 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
199 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
200 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
201 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
202 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
203 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
204 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
205 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
207 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
208 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
209 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
211 #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
212 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
213 #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
214 #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
215 #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
216 #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
218 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
219 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
220 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
223 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
224 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
225 #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
226 #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
227 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
228 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
230 #define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR
231 #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000)
233 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
234 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
236 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
238 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
240 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
243 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
244 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
245 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
246 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
247 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
248 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
249 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
250 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
251 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
253 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
255 #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
258 #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
261 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
263 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
264 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
265 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
266 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
267 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
268 #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
270 #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
272 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
274 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
276 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
277 #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
278 #elif defined(CONFIG_MX6SX)
279 #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
280 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
281 #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
282 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
283 #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
285 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
286 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
287 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
288 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
290 #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
291 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
292 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
293 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
294 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
295 #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
296 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
297 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
300 #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
301 #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
302 #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
303 #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
304 #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
305 #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
306 #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
307 #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
308 #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
309 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
310 #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
311 #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
312 #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
313 #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
314 #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
315 #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
316 #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
317 #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
318 #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
319 #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
320 #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
321 #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
323 /* Only for i.MX6SX */
324 #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
325 #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
326 #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
328 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
329 #define IRAM_SIZE 0x00040000
331 #define IRAM_SIZE 0x00020000
333 #define FEC_QUIRK_ENET_MAC
335 #include <asm/imx-common/regs-lcdif.h>
336 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
337 #include <asm/types.h>
339 /* only for i.MX6SX/UL */
340 #define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \
341 MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
342 #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \
343 MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)
346 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
348 #define SRC_SCR_CORE_1_RESET_OFFSET 14
349 #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
350 #define SRC_SCR_CORE_2_RESET_OFFSET 15
351 #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
352 #define SRC_SCR_CORE_3_RESET_OFFSET 16
353 #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
354 #define SRC_SCR_CORE_1_ENABLE_OFFSET 22
355 #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
356 #define SRC_SCR_CORE_2_ENABLE_OFFSET 23
357 #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
358 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24
359 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
362 u32 vir; /* Version information */
364 u32 stat; /* Status */
365 u32 intctrl; /* Interrupt and Control */
366 u32 intstat; /* Interrupt Status */
368 u32 mda[32]; /* Master Domain Assignment */
370 u32 pdap[104]; /* Peripheral Domain Access Permissions */
373 u32 mrsa; /* Memory Region Start Address */
374 u32 mrea; /* Memory Region End Address */
375 u32 mrc; /* Memory Region Control */
376 u32 mrvs; /* Memory Region Violation Status */
380 struct rdc_sema_regs {
381 u8 gate[64]; /* Gate */
382 u16 rstgt; /* Reset Gate */
422 /* System Reset Controller (SRC) */
443 #define SRC_SCR_M4_ENABLE_OFFSET 22
444 #define SRC_SCR_M4_ENABLE_MASK (1 << 22)
445 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
446 #define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4)
449 #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
450 #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
451 #define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
452 #define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
453 #define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
454 #define IOMUXC_GPR1_DPI_OFF BIT(24)
455 #define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
456 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
457 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
458 #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
459 #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
460 #define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
461 #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
462 #define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
463 #define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
464 #define IOMUXC_GPR1_PCIE_INT BIT(14)
465 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
466 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
467 #define IOMUXC_GPR1_GINT BIT(12)
468 #define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
469 #define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
470 #define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
471 #define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
472 #define IOMUXC_GPR1_ACT_CS3 BIT(9)
473 #define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
474 #define IOMUXC_GPR1_ACT_CS2 BIT(6)
475 #define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
476 #define IOMUXC_GPR1_ACT_CS1 BIT(3)
477 #define IOMUXC_GPR1_ADDRS0_OFFSET (1)
478 #define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
479 #define IOMUXC_GPR1_ACT_CS0 BIT(0)
482 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
483 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
484 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
485 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
486 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
487 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
488 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
489 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
490 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
491 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
492 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
493 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
494 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
495 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
496 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
497 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
498 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
499 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
500 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
501 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
502 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
503 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
504 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
505 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
506 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
507 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
508 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
509 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
511 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
512 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
513 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
514 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
516 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
517 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
519 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
520 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
522 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
523 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
525 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
526 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
528 /* gpr12 bitfields */
529 #define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
530 #define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
531 #define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
532 #define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
533 #define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
534 #define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
535 #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
538 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
557 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
558 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
559 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
560 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
562 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
563 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
564 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
565 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
566 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
567 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
569 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
570 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
571 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
572 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
574 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
575 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
576 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
577 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
579 #define IOMUXC_GPR2_BITMAP_SPWG 0
580 #define IOMUXC_GPR2_BITMAP_JEIDA 1
582 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
583 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
584 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
585 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
587 #define IOMUXC_GPR2_DATA_WIDTH_18 0
588 #define IOMUXC_GPR2_DATA_WIDTH_24 1
590 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
591 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
592 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
593 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
595 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
596 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
597 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
598 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
600 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
601 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
602 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
603 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
605 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
606 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
608 #define IOMUXC_GPR2_MODE_DISABLED 0
609 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
610 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3
612 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
613 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
614 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
615 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
616 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
618 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
619 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
620 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
621 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
622 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
624 /* ECSPI registers */
637 * CSPI register definitions
640 #define MXC_CSPICTRL_EN (1 << 0)
641 #define MXC_CSPICTRL_MODE (1 << 1)
642 #define MXC_CSPICTRL_XCH (1 << 2)
643 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
644 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
645 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
646 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
647 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
648 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
649 #define MXC_CSPICTRL_MAXBITS 0xfff
650 #define MXC_CSPICTRL_TC (1 << 7)
651 #define MXC_CSPICTRL_RXOVF (1 << 6)
652 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
653 #define MAX_SPI_BYTES 32
654 #define SPI_MAX_NUM 4
656 /* Bit position inside CTRL register to be associated with SS */
657 #define MXC_CSPICTRL_CHAN 18
659 /* Bit position inside CON register to be associated with SS */
660 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
661 #define MXC_CSPICON_POL 4 /* SCLK polarity */
662 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
663 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
664 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
665 #define MXC_SPI_BASE_ADDRESSES \
671 #define MXC_SPI_BASE_ADDRESSES \
711 struct fuse_bank0_regs {
730 struct fuse_bank1_regs {
749 struct fuse_bank4_regs {
758 u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
778 u32 pll_sys; /* 0x000 */
779 u32 pll_sys_set; /* 0x004 */
780 u32 pll_sys_clr; /* 0x008 */
781 u32 pll_sys_tog; /* 0x00c */
782 u32 usb1_pll_480_ctrl; /* 0x010 */
783 u32 usb1_pll_480_ctrl_set; /* 0x014 */
784 u32 usb1_pll_480_ctrl_clr; /* 0x018 */
785 u32 usb1_pll_480_ctrl_tog; /* 0x01c */
786 u32 usb2_pll_480_ctrl; /* 0x020 */
787 u32 usb2_pll_480_ctrl_set; /* 0x024 */
788 u32 usb2_pll_480_ctrl_clr; /* 0x028 */
789 u32 usb2_pll_480_ctrl_tog; /* 0x02c */
790 u32 pll_528; /* 0x030 */
791 u32 pll_528_set; /* 0x034 */
792 u32 pll_528_clr; /* 0x038 */
793 u32 pll_528_tog; /* 0x03c */
794 u32 pll_528_ss; /* 0x040 */
796 u32 pll_528_num; /* 0x050 */
798 u32 pll_528_denom; /* 0x060 */
800 u32 pll_audio; /* 0x070 */
801 u32 pll_audio_set; /* 0x074 */
802 u32 pll_audio_clr; /* 0x078 */
803 u32 pll_audio_tog; /* 0x07c */
804 u32 pll_audio_num; /* 0x080 */
806 u32 pll_audio_denom; /* 0x090 */
808 u32 pll_video; /* 0x0a0 */
809 u32 pll_video_set; /* 0x0a4 */
810 u32 pll_video_clr; /* 0x0a8 */
811 u32 pll_video_tog; /* 0x0ac */
812 u32 pll_video_num; /* 0x0b0 */
814 u32 pll_video_denom; /* 0x0c0 */
816 u32 pll_mlb; /* 0x0d0 */
817 u32 pll_mlb_set; /* 0x0d4 */
818 u32 pll_mlb_clr; /* 0x0d8 */
819 u32 pll_mlb_tog; /* 0x0dc */
820 u32 pll_enet; /* 0x0e0 */
821 u32 pll_enet_set; /* 0x0e4 */
822 u32 pll_enet_clr; /* 0x0e8 */
823 u32 pll_enet_tog; /* 0x0ec */
824 u32 pfd_480; /* 0x0f0 */
825 u32 pfd_480_set; /* 0x0f4 */
826 u32 pfd_480_clr; /* 0x0f8 */
827 u32 pfd_480_tog; /* 0x0fc */
828 u32 pfd_528; /* 0x100 */
829 u32 pfd_528_set; /* 0x104 */
830 u32 pfd_528_clr; /* 0x108 */
831 u32 pfd_528_tog; /* 0x10c */
832 u32 reg_1p1; /* 0x110 */
833 u32 reg_1p1_set; /* 0x114 */
834 u32 reg_1p1_clr; /* 0x118 */
835 u32 reg_1p1_tog; /* 0x11c */
836 u32 reg_3p0; /* 0x120 */
837 u32 reg_3p0_set; /* 0x124 */
838 u32 reg_3p0_clr; /* 0x128 */
839 u32 reg_3p0_tog; /* 0x12c */
840 u32 reg_2p5; /* 0x130 */
841 u32 reg_2p5_set; /* 0x134 */
842 u32 reg_2p5_clr; /* 0x138 */
843 u32 reg_2p5_tog; /* 0x13c */
844 u32 reg_core; /* 0x140 */
845 u32 reg_core_set; /* 0x144 */
846 u32 reg_core_clr; /* 0x148 */
847 u32 reg_core_tog; /* 0x14c */
848 u32 ana_misc0; /* 0x150 */
849 u32 ana_misc0_set; /* 0x154 */
850 u32 ana_misc0_clr; /* 0x158 */
851 u32 ana_misc0_tog; /* 0x15c */
852 u32 ana_misc1; /* 0x160 */
853 u32 ana_misc1_set; /* 0x164 */
854 u32 ana_misc1_clr; /* 0x168 */
855 u32 ana_misc1_tog; /* 0x16c */
856 u32 ana_misc2; /* 0x170 */
857 u32 ana_misc2_set; /* 0x174 */
858 u32 ana_misc2_clr; /* 0x178 */
859 u32 ana_misc2_tog; /* 0x17c */
860 u32 tempsense0; /* 0x180 */
861 u32 tempsense0_set; /* 0x184 */
862 u32 tempsense0_clr; /* 0x188 */
863 u32 tempsense0_tog; /* 0x18c */
864 u32 tempsense1; /* 0x190 */
865 u32 tempsense1_set; /* 0x194 */
866 u32 tempsense1_clr; /* 0x198 */
867 u32 tempsense1_tog; /* 0x19c */
868 u32 usb1_vbus_detect; /* 0x1a0 */
869 u32 usb1_vbus_detect_set; /* 0x1a4 */
870 u32 usb1_vbus_detect_clr; /* 0x1a8 */
871 u32 usb1_vbus_detect_tog; /* 0x1ac */
872 u32 usb1_chrg_detect; /* 0x1b0 */
873 u32 usb1_chrg_detect_set; /* 0x1b4 */
874 u32 usb1_chrg_detect_clr; /* 0x1b8 */
875 u32 usb1_chrg_detect_tog; /* 0x1bc */
876 u32 usb1_vbus_det_stat; /* 0x1c0 */
877 u32 usb1_vbus_det_stat_set; /* 0x1c4 */
878 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
879 u32 usb1_vbus_det_stat_tog; /* 0x1cc */
880 u32 usb1_chrg_det_stat; /* 0x1d0 */
881 u32 usb1_chrg_det_stat_set; /* 0x1d4 */
882 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
883 u32 usb1_chrg_det_stat_tog; /* 0x1dc */
884 u32 usb1_loopback; /* 0x1e0 */
885 u32 usb1_loopback_set; /* 0x1e4 */
886 u32 usb1_loopback_clr; /* 0x1e8 */
887 u32 usb1_loopback_tog; /* 0x1ec */
888 u32 usb1_misc; /* 0x1f0 */
889 u32 usb1_misc_set; /* 0x1f4 */
890 u32 usb1_misc_clr; /* 0x1f8 */
891 u32 usb1_misc_tog; /* 0x1fc */
892 u32 usb2_vbus_detect; /* 0x200 */
893 u32 usb2_vbus_detect_set; /* 0x204 */
894 u32 usb2_vbus_detect_clr; /* 0x208 */
895 u32 usb2_vbus_detect_tog; /* 0x20c */
896 u32 usb2_chrg_detect; /* 0x210 */
897 u32 usb2_chrg_detect_set; /* 0x214 */
898 u32 usb2_chrg_detect_clr; /* 0x218 */
899 u32 usb2_chrg_detect_tog; /* 0x21c */
900 u32 usb2_vbus_det_stat; /* 0x220 */
901 u32 usb2_vbus_det_stat_set; /* 0x224 */
902 u32 usb2_vbus_det_stat_clr; /* 0x228 */
903 u32 usb2_vbus_det_stat_tog; /* 0x22c */
904 u32 usb2_chrg_det_stat; /* 0x230 */
905 u32 usb2_chrg_det_stat_set; /* 0x234 */
906 u32 usb2_chrg_det_stat_clr; /* 0x238 */
907 u32 usb2_chrg_det_stat_tog; /* 0x23c */
908 u32 usb2_loopback; /* 0x240 */
909 u32 usb2_loopback_set; /* 0x244 */
910 u32 usb2_loopback_clr; /* 0x248 */
911 u32 usb2_loopback_tog; /* 0x24c */
912 u32 usb2_misc; /* 0x250 */
913 u32 usb2_misc_set; /* 0x254 */
914 u32 usb2_misc_clr; /* 0x258 */
915 u32 usb2_misc_tog; /* 0x25c */
916 u32 digprog; /* 0x260 */
918 u32 digprog_sololite; /* 0x280 */
921 #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
922 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
923 #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
924 #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
925 #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
926 #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
929 u16 wcr; /* Control */
930 u16 wsr; /* Service */
931 u16 wrsr; /* Reset Status */
932 u16 wicr; /* Interrupt Control */
933 u16 wmcr; /* Miscellaneous Control */
936 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
937 #define PWMCR_DOZEEN (1 << 24)
938 #define PWMCR_WAITEN (1 << 23)
939 #define PWMCR_DBGEN (1 << 22)
940 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
941 #define PWMCR_CLKSRC_IPG (1 << 16)
942 #define PWMCR_EN (1 << 0)
952 #endif /* __ASSEMBLER__*/
953 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */