2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x000FFFFF
16 #define GPU_2D_ARB_BASE_ADDR 0x02200000
17 #define GPU_2D_ARB_END_ADDR 0x02203FFF
18 #define OPENVG_ARB_BASE_ADDR 0x02204000
19 #define OPENVG_ARB_END_ADDR 0x02207FFF
20 #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
21 #define CAAM_ARB_BASE_ADDR 0x00100000
22 #define CAAM_ARB_END_ADDR 0x00107FFF
23 #define GPU_ARB_BASE_ADDR 0x01800000
24 #define GPU_ARB_END_ADDR 0x01803FFF
25 #define APBH_DMA_ARB_BASE_ADDR 0x01804000
26 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
27 #define M4_BOOTROM_BASE_ADDR 0x007F8000
29 #elif !defined(CONFIG_MX6SLL)
30 #define CAAM_ARB_BASE_ADDR 0x00100000
31 #define CAAM_ARB_END_ADDR 0x00103FFF
32 #define APBH_DMA_ARB_BASE_ADDR 0x00110000
33 #define APBH_DMA_ARB_END_ADDR 0x00117FFF
34 #define HDMI_ARB_BASE_ADDR 0x00120000
35 #define HDMI_ARB_END_ADDR 0x00128FFF
36 #define GPU_3D_ARB_BASE_ADDR 0x00130000
37 #define GPU_3D_ARB_END_ADDR 0x00133FFF
38 #define GPU_2D_ARB_BASE_ADDR 0x00134000
39 #define GPU_2D_ARB_END_ADDR 0x00137FFF
40 #define DTCP_ARB_BASE_ADDR 0x00138000
41 #define DTCP_ARB_END_ADDR 0x0013BFFF
42 #endif /* CONFIG_MX6SL */
44 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
45 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
46 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
48 /* GPV - PL301 configuration ports */
49 #if (defined(CONFIG_MX6SX) || \
50 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
51 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
52 #define GPV2_BASE_ADDR 0x00D00000
53 #define GPV3_BASE_ADDR 0x00E00000
54 #define GPV4_BASE_ADDR 0x00F00000
55 #define GPV5_BASE_ADDR 0x01000000
56 #define GPV6_BASE_ADDR 0x01100000
57 #define PCIE_ARB_BASE_ADDR 0x08000000
58 #define PCIE_ARB_END_ADDR 0x08FFFFFF
61 #define GPV2_BASE_ADDR 0x00200000
62 #define GPV3_BASE_ADDR 0x00300000
63 #define GPV4_BASE_ADDR 0x00800000
64 #define PCIE_ARB_BASE_ADDR 0x01000000
65 #define PCIE_ARB_END_ADDR 0x01FFFFFF
68 #define IRAM_BASE_ADDR 0x00900000
69 #define SCU_BASE_ADDR 0x00A00000
70 #define IC_INTERFACES_BASE_ADDR 0x00A00100
71 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
72 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
73 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
74 #define L2_PL310_BASE 0x00A02000
75 #define GPV0_BASE_ADDR 0x00B00000
76 #define GPV1_BASE_ADDR 0x00C00000
78 #define AIPS1_ARB_BASE_ADDR 0x02000000
79 #define AIPS1_ARB_END_ADDR 0x020FFFFF
80 #define AIPS2_ARB_BASE_ADDR 0x02100000
81 #define AIPS2_ARB_END_ADDR 0x021FFFFF
82 /* AIPS3 only on i.MX6SX */
83 #define AIPS3_ARB_BASE_ADDR 0x02200000
84 #define AIPS3_ARB_END_ADDR 0x022FFFFF
86 #define WEIM_ARB_BASE_ADDR 0x50000000
87 #define WEIM_ARB_END_ADDR 0x57FFFFFF
88 #define QSPI0_AMBA_BASE 0x60000000
89 #define QSPI0_AMBA_END 0x6FFFFFFF
90 #define QSPI1_AMBA_BASE 0x70000000
91 #define QSPI1_AMBA_END 0x7FFFFFFF
92 #elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
93 #define WEIM_ARB_BASE_ADDR 0x50000000
94 #define WEIM_ARB_END_ADDR 0x57FFFFFF
95 #define QSPI0_AMBA_BASE 0x60000000
96 #define QSPI0_AMBA_END 0x6FFFFFFF
97 #elif !defined(CONFIG_MX6SLL)
98 #define SATA_ARB_BASE_ADDR 0x02200000
99 #define SATA_ARB_END_ADDR 0x02203FFF
100 #define OPENVG_ARB_BASE_ADDR 0x02204000
101 #define OPENVG_ARB_END_ADDR 0x02207FFF
102 #define HSI_ARB_BASE_ADDR 0x02208000
103 #define HSI_ARB_END_ADDR 0x0220BFFF
104 #define IPU1_ARB_BASE_ADDR 0x02400000
105 #define IPU1_ARB_END_ADDR 0x027FFFFF
106 #define IPU2_ARB_BASE_ADDR 0x02800000
107 #define IPU2_ARB_END_ADDR 0x02BFFFFF
108 #define WEIM_ARB_BASE_ADDR 0x08000000
109 #define WEIM_ARB_END_ADDR 0x0FFFFFFF
112 #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
113 defined(CONFIG_MX6SX) || \
114 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
115 #define MMDC0_ARB_BASE_ADDR 0x80000000
116 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
117 #define MMDC1_ARB_BASE_ADDR 0xC0000000
118 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
120 #define MMDC0_ARB_BASE_ADDR 0x10000000
121 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
122 #define MMDC1_ARB_BASE_ADDR 0x80000000
123 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
127 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
128 #define IPU_SOC_OFFSET 0x00200000
131 /* Defines for Blocks connected via AIPS (SkyBlue) */
132 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
133 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
134 #define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
135 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
136 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
137 #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
139 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
140 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
141 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
142 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
143 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
145 #define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
146 #define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
147 #define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
148 #define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
149 #define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
150 #define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
151 #define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
152 #define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
153 #define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
156 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
158 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
159 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
160 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
161 #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
162 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
163 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
164 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
165 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
168 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
169 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
171 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
173 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
174 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
175 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
176 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
177 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
178 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
179 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
180 /* QOSC on i.MX6SLL */
181 #define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
182 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
183 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
184 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
185 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
186 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
187 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
188 #define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
189 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
190 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
191 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
192 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
193 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
194 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
195 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
196 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
197 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
198 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
199 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
200 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
201 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
202 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
203 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
204 #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
206 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
207 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
208 #define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
209 #define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
210 #define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
211 #elif defined(CONFIG_MX6SL)
212 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
213 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
214 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
215 #elif defined(CONFIG_MX6SX)
216 #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
217 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
218 #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
219 #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
220 #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
221 #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
223 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
224 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
225 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
228 #define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
229 #define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
231 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
232 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
233 #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
234 #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
235 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
236 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
238 #define CONFIG_SYS_FSL_SEC_OFFSET 0
239 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
240 CONFIG_SYS_FSL_SEC_OFFSET)
241 #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
242 #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
243 CONFIG_SYS_FSL_JR0_OFFSET)
244 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
246 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
247 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
249 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
251 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
253 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
257 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
258 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
259 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
260 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
261 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
262 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
263 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
264 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
266 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
267 #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
268 #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
271 #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
274 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
276 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
277 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
278 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
280 #define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
281 #define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
283 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
284 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
285 #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
286 #define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
288 #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
290 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
292 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
293 #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
294 #define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
295 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
296 #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
297 #elif defined(CONFIG_MX6SX)
298 #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
299 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
300 #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
301 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
302 #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
304 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
305 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
306 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
307 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
309 #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
310 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
311 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
312 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
313 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
314 #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
315 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
316 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
318 #define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
321 #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
322 #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
323 #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
324 #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
325 #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
326 #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
327 #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
328 #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
329 #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
330 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
331 #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
332 #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
333 #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
334 #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
335 #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
336 #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
337 #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
338 #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
339 #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
340 #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
341 #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
342 #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
343 #elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
344 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
345 #define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
346 #define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
347 #define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
348 #define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
349 #define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
350 #define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
353 #define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000)
355 /* Only for i.MX6SX */
356 #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
357 #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
358 #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
360 #if !(defined(CONFIG_MX6SX) || \
361 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
362 defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
363 #define IRAM_SIZE 0x00040000
365 #define IRAM_SIZE 0x00020000
367 #define FEC_QUIRK_ENET_MAC
369 #include <asm/mach-imx/regs-lcdif.h>
370 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
371 #include <asm/types.h>
373 /* only for i.MX6SX/UL */
374 #define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \
375 MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
376 #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
377 MX6SLL_LCDIF_BASE_ADDR : \
378 (is_cpu_type(MXC_CPU_MX6SL)) ? \
379 MX6SL_LCDIF_BASE_ADDR : \
380 ((is_cpu_type(MXC_CPU_MX6UL)) ? \
381 MX6UL_LCDIF1_BASE_ADDR : \
383 MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
386 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
388 #define SRC_SCR_CORE_1_RESET_OFFSET 14
389 #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
390 #define SRC_SCR_CORE_2_RESET_OFFSET 15
391 #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
392 #define SRC_SCR_CORE_3_RESET_OFFSET 16
393 #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
394 #define SRC_SCR_CORE_1_ENABLE_OFFSET 22
395 #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
396 #define SRC_SCR_CORE_2_ENABLE_OFFSET 23
397 #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
398 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24
399 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
402 u32 vir; /* Version information */
404 u32 stat; /* Status */
405 u32 intctrl; /* Interrupt and Control */
406 u32 intstat; /* Interrupt Status */
408 u32 mda[32]; /* Master Domain Assignment */
410 u32 pdap[104]; /* Peripheral Domain Access Permissions */
413 u32 mrsa; /* Memory Region Start Address */
414 u32 mrea; /* Memory Region End Address */
415 u32 mrc; /* Memory Region Control */
416 u32 mrvs; /* Memory Region Violation Status */
420 struct rdc_sema_regs {
421 u8 gate[64]; /* Gate */
422 u16 rstgt; /* Reset Gate */
462 /* System Reset Controller (SRC) */
483 #define src_base ((struct src *)SRC_BASE_ADDR)
485 #define SRC_SCR_M4_ENABLE_OFFSET 22
486 #define SRC_SCR_M4_ENABLE_MASK (1 << 22)
487 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
488 #define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4)
491 #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
492 #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
493 #define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
494 #define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
495 #define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
496 #define IOMUXC_GPR1_DPI_OFF BIT(24)
497 #define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
498 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
499 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
500 #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
501 #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
502 #define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
503 #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
504 #define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
505 #define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
506 #define IOMUXC_GPR1_PCIE_INT BIT(14)
507 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
508 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
509 #define IOMUXC_GPR1_GINT BIT(12)
510 #define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
511 #define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
512 #define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
513 #define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
514 #define IOMUXC_GPR1_ACT_CS3 BIT(9)
515 #define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
516 #define IOMUXC_GPR1_ACT_CS2 BIT(6)
517 #define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
518 #define IOMUXC_GPR1_ACT_CS1 BIT(3)
519 #define IOMUXC_GPR1_ADDRS0_OFFSET (1)
520 #define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
521 #define IOMUXC_GPR1_ACT_CS0 BIT(0)
524 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
525 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
526 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
527 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
528 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
529 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
530 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
531 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
532 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
533 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
534 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
535 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
536 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
537 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
538 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
539 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
540 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
541 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
542 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
543 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
544 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
545 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
546 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
547 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
548 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
549 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
550 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
551 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
553 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
554 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
555 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
556 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
558 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
559 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
561 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
562 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
564 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
565 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
567 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
568 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
570 /* gpr12 bitfields */
571 #define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
572 #define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
573 #define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
574 #define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
575 #define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
576 #define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
577 #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
580 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
599 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
600 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
601 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
602 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
604 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
605 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
606 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
607 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
608 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
609 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
611 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
612 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
613 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
614 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
616 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
617 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
618 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
619 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
621 #define IOMUXC_GPR2_BITMAP_SPWG 0
622 #define IOMUXC_GPR2_BITMAP_JEIDA 1
624 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
625 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
626 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
627 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
629 #define IOMUXC_GPR2_DATA_WIDTH_18 0
630 #define IOMUXC_GPR2_DATA_WIDTH_24 1
632 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
633 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
634 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
635 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
637 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
638 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
639 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
640 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
642 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
643 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
644 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
645 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
647 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
648 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
650 #define IOMUXC_GPR2_MODE_DISABLED 0
651 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
652 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3
654 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
655 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
656 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
657 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
658 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
660 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
661 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
662 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
663 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
664 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
666 /* ECSPI registers */
679 * CSPI register definitions
682 #define MXC_CSPICTRL_EN (1 << 0)
683 #define MXC_CSPICTRL_MODE (1 << 1)
684 #define MXC_CSPICTRL_XCH (1 << 2)
685 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
686 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
687 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
688 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
689 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
690 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
691 #define MXC_CSPICTRL_MAXBITS 0xfff
692 #define MXC_CSPICTRL_TC (1 << 7)
693 #define MXC_CSPICTRL_RXOVF (1 << 6)
694 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
695 #define MAX_SPI_BYTES 32
696 #define SPI_MAX_NUM 4
698 /* Bit position inside CTRL register to be associated with SS */
699 #define MXC_CSPICTRL_CHAN 18
701 /* Bit position inside CON register to be associated with SS */
702 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
703 #define MXC_CSPICON_POL 4 /* SCLK polarity */
704 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
705 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
706 #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
707 defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
708 #define MXC_SPI_BASE_ADDRESSES \
714 #define MXC_SPI_BASE_ADDRESSES \
754 struct fuse_bank0_regs {
773 struct fuse_bank1_regs {
792 struct fuse_bank4_regs {
801 u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
821 u32 pll_sys; /* 0x000 */
822 u32 pll_sys_set; /* 0x004 */
823 u32 pll_sys_clr; /* 0x008 */
824 u32 pll_sys_tog; /* 0x00c */
825 u32 usb1_pll_480_ctrl; /* 0x010 */
826 u32 usb1_pll_480_ctrl_set; /* 0x014 */
827 u32 usb1_pll_480_ctrl_clr; /* 0x018 */
828 u32 usb1_pll_480_ctrl_tog; /* 0x01c */
829 u32 usb2_pll_480_ctrl; /* 0x020 */
830 u32 usb2_pll_480_ctrl_set; /* 0x024 */
831 u32 usb2_pll_480_ctrl_clr; /* 0x028 */
832 u32 usb2_pll_480_ctrl_tog; /* 0x02c */
833 u32 pll_528; /* 0x030 */
834 u32 pll_528_set; /* 0x034 */
835 u32 pll_528_clr; /* 0x038 */
836 u32 pll_528_tog; /* 0x03c */
837 u32 pll_528_ss; /* 0x040 */
839 u32 pll_528_num; /* 0x050 */
841 u32 pll_528_denom; /* 0x060 */
843 u32 pll_audio; /* 0x070 */
844 u32 pll_audio_set; /* 0x074 */
845 u32 pll_audio_clr; /* 0x078 */
846 u32 pll_audio_tog; /* 0x07c */
847 u32 pll_audio_num; /* 0x080 */
849 u32 pll_audio_denom; /* 0x090 */
851 u32 pll_video; /* 0x0a0 */
852 u32 pll_video_set; /* 0x0a4 */
853 u32 pll_video_clr; /* 0x0a8 */
854 u32 pll_video_tog; /* 0x0ac */
855 u32 pll_video_num; /* 0x0b0 */
857 u32 pll_video_denom; /* 0x0c0 */
859 u32 pll_mlb; /* 0x0d0 */
860 u32 pll_mlb_set; /* 0x0d4 */
861 u32 pll_mlb_clr; /* 0x0d8 */
862 u32 pll_mlb_tog; /* 0x0dc */
863 u32 pll_enet; /* 0x0e0 */
864 u32 pll_enet_set; /* 0x0e4 */
865 u32 pll_enet_clr; /* 0x0e8 */
866 u32 pll_enet_tog; /* 0x0ec */
867 u32 pfd_480; /* 0x0f0 */
868 u32 pfd_480_set; /* 0x0f4 */
869 u32 pfd_480_clr; /* 0x0f8 */
870 u32 pfd_480_tog; /* 0x0fc */
871 u32 pfd_528; /* 0x100 */
872 u32 pfd_528_set; /* 0x104 */
873 u32 pfd_528_clr; /* 0x108 */
874 u32 pfd_528_tog; /* 0x10c */
875 u32 reg_1p1; /* 0x110 */
876 u32 reg_1p1_set; /* 0x114 */
877 u32 reg_1p1_clr; /* 0x118 */
878 u32 reg_1p1_tog; /* 0x11c */
879 u32 reg_3p0; /* 0x120 */
880 u32 reg_3p0_set; /* 0x124 */
881 u32 reg_3p0_clr; /* 0x128 */
882 u32 reg_3p0_tog; /* 0x12c */
883 u32 reg_2p5; /* 0x130 */
884 u32 reg_2p5_set; /* 0x134 */
885 u32 reg_2p5_clr; /* 0x138 */
886 u32 reg_2p5_tog; /* 0x13c */
887 u32 reg_core; /* 0x140 */
888 u32 reg_core_set; /* 0x144 */
889 u32 reg_core_clr; /* 0x148 */
890 u32 reg_core_tog; /* 0x14c */
891 u32 ana_misc0; /* 0x150 */
892 u32 ana_misc0_set; /* 0x154 */
893 u32 ana_misc0_clr; /* 0x158 */
894 u32 ana_misc0_tog; /* 0x15c */
895 u32 ana_misc1; /* 0x160 */
896 u32 ana_misc1_set; /* 0x164 */
897 u32 ana_misc1_clr; /* 0x168 */
898 u32 ana_misc1_tog; /* 0x16c */
899 u32 ana_misc2; /* 0x170 */
900 u32 ana_misc2_set; /* 0x174 */
901 u32 ana_misc2_clr; /* 0x178 */
902 u32 ana_misc2_tog; /* 0x17c */
903 u32 tempsense0; /* 0x180 */
904 u32 tempsense0_set; /* 0x184 */
905 u32 tempsense0_clr; /* 0x188 */
906 u32 tempsense0_tog; /* 0x18c */
907 u32 tempsense1; /* 0x190 */
908 u32 tempsense1_set; /* 0x194 */
909 u32 tempsense1_clr; /* 0x198 */
910 u32 tempsense1_tog; /* 0x19c */
911 u32 usb1_vbus_detect; /* 0x1a0 */
912 u32 usb1_vbus_detect_set; /* 0x1a4 */
913 u32 usb1_vbus_detect_clr; /* 0x1a8 */
914 u32 usb1_vbus_detect_tog; /* 0x1ac */
915 u32 usb1_chrg_detect; /* 0x1b0 */
916 u32 usb1_chrg_detect_set; /* 0x1b4 */
917 u32 usb1_chrg_detect_clr; /* 0x1b8 */
918 u32 usb1_chrg_detect_tog; /* 0x1bc */
919 u32 usb1_vbus_det_stat; /* 0x1c0 */
920 u32 usb1_vbus_det_stat_set; /* 0x1c4 */
921 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
922 u32 usb1_vbus_det_stat_tog; /* 0x1cc */
923 u32 usb1_chrg_det_stat; /* 0x1d0 */
924 u32 usb1_chrg_det_stat_set; /* 0x1d4 */
925 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
926 u32 usb1_chrg_det_stat_tog; /* 0x1dc */
927 u32 usb1_loopback; /* 0x1e0 */
928 u32 usb1_loopback_set; /* 0x1e4 */
929 u32 usb1_loopback_clr; /* 0x1e8 */
930 u32 usb1_loopback_tog; /* 0x1ec */
931 u32 usb1_misc; /* 0x1f0 */
932 u32 usb1_misc_set; /* 0x1f4 */
933 u32 usb1_misc_clr; /* 0x1f8 */
934 u32 usb1_misc_tog; /* 0x1fc */
935 u32 usb2_vbus_detect; /* 0x200 */
936 u32 usb2_vbus_detect_set; /* 0x204 */
937 u32 usb2_vbus_detect_clr; /* 0x208 */
938 u32 usb2_vbus_detect_tog; /* 0x20c */
939 u32 usb2_chrg_detect; /* 0x210 */
940 u32 usb2_chrg_detect_set; /* 0x214 */
941 u32 usb2_chrg_detect_clr; /* 0x218 */
942 u32 usb2_chrg_detect_tog; /* 0x21c */
943 u32 usb2_vbus_det_stat; /* 0x220 */
944 u32 usb2_vbus_det_stat_set; /* 0x224 */
945 u32 usb2_vbus_det_stat_clr; /* 0x228 */
946 u32 usb2_vbus_det_stat_tog; /* 0x22c */
947 u32 usb2_chrg_det_stat; /* 0x230 */
948 u32 usb2_chrg_det_stat_set; /* 0x234 */
949 u32 usb2_chrg_det_stat_clr; /* 0x238 */
950 u32 usb2_chrg_det_stat_tog; /* 0x23c */
951 u32 usb2_loopback; /* 0x240 */
952 u32 usb2_loopback_set; /* 0x244 */
953 u32 usb2_loopback_clr; /* 0x248 */
954 u32 usb2_loopback_tog; /* 0x24c */
955 u32 usb2_misc; /* 0x250 */
956 u32 usb2_misc_set; /* 0x254 */
957 u32 usb2_misc_clr; /* 0x258 */
958 u32 usb2_misc_tog; /* 0x25c */
959 u32 digprog; /* 0x260 */
961 u32 digprog_sololite; /* 0x280 */
964 #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
965 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
966 #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
967 #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
968 #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
969 #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
972 u16 wcr; /* Control */
973 u16 wsr; /* Service */
974 u16 wrsr; /* Reset Status */
975 u16 wicr; /* Interrupt Control */
976 u16 wmcr; /* Miscellaneous Control */
979 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
980 #define PWMCR_DOZEEN (1 << 24)
981 #define PWMCR_WAITEN (1 << 23)
982 #define PWMCR_DBGEN (1 << 22)
983 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
984 #define PWMCR_CLKSRC_IPG (1 << 16)
985 #define PWMCR_EN (1 << 0)
995 #endif /* __ASSEMBLER__*/
996 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */