2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x000FFFFF
16 #define GPU_2D_ARB_BASE_ADDR 0x02200000
17 #define GPU_2D_ARB_END_ADDR 0x02203FFF
18 #define OPENVG_ARB_BASE_ADDR 0x02204000
19 #define OPENVG_ARB_END_ADDR 0x02207FFF
20 #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
21 #define CAAM_ARB_BASE_ADDR 0x00100000
22 #define CAAM_ARB_END_ADDR 0x00107FFF
23 #define GPU_ARB_BASE_ADDR 0x01800000
24 #define GPU_ARB_END_ADDR 0x01803FFF
25 #define APBH_DMA_ARB_BASE_ADDR 0x01804000
26 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
27 #define M4_BOOTROM_BASE_ADDR 0x007F8000
29 #elif !defined(CONFIG_MX6SLL)
30 #define CAAM_ARB_BASE_ADDR 0x00100000
31 #define CAAM_ARB_END_ADDR 0x00103FFF
32 #define APBH_DMA_ARB_BASE_ADDR 0x00110000
33 #define APBH_DMA_ARB_END_ADDR 0x00117FFF
34 #define HDMI_ARB_BASE_ADDR 0x00120000
35 #define HDMI_ARB_END_ADDR 0x00128FFF
36 #define GPU_3D_ARB_BASE_ADDR 0x00130000
37 #define GPU_3D_ARB_END_ADDR 0x00133FFF
38 #define GPU_2D_ARB_BASE_ADDR 0x00134000
39 #define GPU_2D_ARB_END_ADDR 0x00137FFF
40 #define DTCP_ARB_BASE_ADDR 0x00138000
41 #define DTCP_ARB_END_ADDR 0x0013BFFF
42 #endif /* CONFIG_MX6SL */
44 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
45 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
46 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
48 /* GPV - PL301 configuration ports */
49 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
50 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
51 #define GPV2_BASE_ADDR 0x00D00000
52 #define GPV3_BASE_ADDR 0x00E00000
53 #define GPV4_BASE_ADDR 0x00F00000
54 #define GPV5_BASE_ADDR 0x01000000
55 #define GPV6_BASE_ADDR 0x01100000
56 #define PCIE_ARB_BASE_ADDR 0x08000000
57 #define PCIE_ARB_END_ADDR 0x08FFFFFF
60 #define GPV2_BASE_ADDR 0x00200000
61 #define GPV3_BASE_ADDR 0x00300000
62 #define GPV4_BASE_ADDR 0x00800000
63 #define PCIE_ARB_BASE_ADDR 0x01000000
64 #define PCIE_ARB_END_ADDR 0x01FFFFFF
67 #define IRAM_BASE_ADDR 0x00900000
68 #define SCU_BASE_ADDR 0x00A00000
69 #define IC_INTERFACES_BASE_ADDR 0x00A00100
70 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
71 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
72 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
73 #define L2_PL310_BASE 0x00A02000
74 #define GPV0_BASE_ADDR 0x00B00000
75 #define GPV1_BASE_ADDR 0x00C00000
77 #define AIPS1_ARB_BASE_ADDR 0x02000000
78 #define AIPS1_ARB_END_ADDR 0x020FFFFF
79 #define AIPS2_ARB_BASE_ADDR 0x02100000
80 #define AIPS2_ARB_END_ADDR 0x021FFFFF
81 /* AIPS3 only on i.MX6SX */
82 #define AIPS3_ARB_BASE_ADDR 0x02200000
83 #define AIPS3_ARB_END_ADDR 0x022FFFFF
85 #define WEIM_ARB_BASE_ADDR 0x50000000
86 #define WEIM_ARB_END_ADDR 0x57FFFFFF
87 #define QSPI0_AMBA_BASE 0x60000000
88 #define QSPI0_AMBA_END 0x6FFFFFFF
89 #define QSPI1_AMBA_BASE 0x70000000
90 #define QSPI1_AMBA_END 0x7FFFFFFF
91 #elif defined(CONFIG_MX6UL)
92 #define WEIM_ARB_BASE_ADDR 0x50000000
93 #define WEIM_ARB_END_ADDR 0x57FFFFFF
94 #define QSPI0_AMBA_BASE 0x60000000
95 #define QSPI0_AMBA_END 0x6FFFFFFF
96 #elif !defined(CONFIG_MX6SLL)
97 #define SATA_ARB_BASE_ADDR 0x02200000
98 #define SATA_ARB_END_ADDR 0x02203FFF
99 #define OPENVG_ARB_BASE_ADDR 0x02204000
100 #define OPENVG_ARB_END_ADDR 0x02207FFF
101 #define HSI_ARB_BASE_ADDR 0x02208000
102 #define HSI_ARB_END_ADDR 0x0220BFFF
103 #define IPU1_ARB_BASE_ADDR 0x02400000
104 #define IPU1_ARB_END_ADDR 0x027FFFFF
105 #define IPU2_ARB_BASE_ADDR 0x02800000
106 #define IPU2_ARB_END_ADDR 0x02BFFFFF
107 #define WEIM_ARB_BASE_ADDR 0x08000000
108 #define WEIM_ARB_END_ADDR 0x0FFFFFFF
111 #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
112 defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
113 #define MMDC0_ARB_BASE_ADDR 0x80000000
114 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
115 #define MMDC1_ARB_BASE_ADDR 0xC0000000
116 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
118 #define MMDC0_ARB_BASE_ADDR 0x10000000
119 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
120 #define MMDC1_ARB_BASE_ADDR 0x80000000
121 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
125 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
126 #define IPU_SOC_OFFSET 0x00200000
129 /* Defines for Blocks connected via AIPS (SkyBlue) */
130 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
131 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
132 #define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
133 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
134 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
135 #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
137 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
138 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
139 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
140 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
141 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
143 #define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
144 #define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
145 #define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
146 #define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
147 #define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
148 #define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
149 #define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
150 #define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
151 #define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
154 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
156 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
157 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
158 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
159 #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
160 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
161 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
162 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
163 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
166 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
167 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
169 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
171 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
172 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
173 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
174 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
175 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
176 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
177 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
178 /* QOSC on i.MX6SLL */
179 #define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
180 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
181 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
182 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
183 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
184 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
185 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
186 #define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
187 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
188 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
189 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
190 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
191 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
192 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
193 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
194 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
195 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
196 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
197 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
198 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
199 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
200 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
201 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
202 #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
204 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
205 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
206 #define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
207 #define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
208 #define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
209 #elif defined(CONFIG_MX6SL)
210 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
211 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
212 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
213 #elif defined(CONFIG_MX6SX)
214 #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
215 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
216 #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
217 #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
218 #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
219 #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
221 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
222 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
223 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
226 #define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
227 #define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
229 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
230 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
231 #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
232 #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
233 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
234 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
236 #define CONFIG_SYS_FSL_SEC_OFFSET 0
237 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
238 CONFIG_SYS_FSL_SEC_OFFSET)
239 #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
240 #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
241 CONFIG_SYS_FSL_JR0_OFFSET)
242 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
244 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
245 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
247 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
249 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
251 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
254 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
255 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
256 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
257 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
258 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
259 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
260 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
261 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
262 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
264 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
266 #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
269 #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
272 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
274 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
275 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
276 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
278 #define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
279 #define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
281 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
282 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
283 #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
284 #define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
286 #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
288 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
290 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
292 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
293 #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
294 #elif defined(CONFIG_MX6SX)
295 #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
296 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
297 #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
298 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
299 #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
301 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
302 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
303 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
304 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
306 #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
307 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
308 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
309 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
310 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
311 #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
312 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
313 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
315 #define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
318 #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
319 #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
320 #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
321 #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
322 #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
323 #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
324 #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
325 #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
326 #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
327 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
328 #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
329 #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
330 #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
331 #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
332 #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
333 #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
334 #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
335 #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
336 #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
337 #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
338 #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
339 #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
340 #elif defined(CONFIG_MX6ULL)
341 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
342 #define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
343 #define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
344 #define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
345 #define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
346 #define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
347 #define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
349 /* Only for i.MX6SX */
350 #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
351 #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
352 #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
354 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
355 defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
356 #define IRAM_SIZE 0x00040000
358 #define IRAM_SIZE 0x00020000
360 #define FEC_QUIRK_ENET_MAC
362 #include <asm/imx-common/regs-lcdif.h>
363 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
364 #include <asm/types.h>
366 /* only for i.MX6SX/UL */
367 #define WDOG3_BASE_ADDR ((is_mx6ul() ? \
368 MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
369 #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
370 MX6SLL_LCDIF_BASE_ADDR : \
371 (is_cpu_type(MXC_CPU_MX6SL)) ? \
372 MX6SL_LCDIF_BASE_ADDR : \
373 ((is_cpu_type(MXC_CPU_MX6UL)) ? \
374 MX6UL_LCDIF1_BASE_ADDR : \
376 MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
379 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
381 #define SRC_SCR_CORE_1_RESET_OFFSET 14
382 #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
383 #define SRC_SCR_CORE_2_RESET_OFFSET 15
384 #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
385 #define SRC_SCR_CORE_3_RESET_OFFSET 16
386 #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
387 #define SRC_SCR_CORE_1_ENABLE_OFFSET 22
388 #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
389 #define SRC_SCR_CORE_2_ENABLE_OFFSET 23
390 #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
391 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24
392 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
395 u32 vir; /* Version information */
397 u32 stat; /* Status */
398 u32 intctrl; /* Interrupt and Control */
399 u32 intstat; /* Interrupt Status */
401 u32 mda[32]; /* Master Domain Assignment */
403 u32 pdap[104]; /* Peripheral Domain Access Permissions */
406 u32 mrsa; /* Memory Region Start Address */
407 u32 mrea; /* Memory Region End Address */
408 u32 mrc; /* Memory Region Control */
409 u32 mrvs; /* Memory Region Violation Status */
413 struct rdc_sema_regs {
414 u8 gate[64]; /* Gate */
415 u16 rstgt; /* Reset Gate */
455 /* System Reset Controller (SRC) */
476 #define src_base ((struct src *)SRC_BASE_ADDR)
478 #define SRC_SCR_M4_ENABLE_OFFSET 22
479 #define SRC_SCR_M4_ENABLE_MASK (1 << 22)
480 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
481 #define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4)
484 #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
485 #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
486 #define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
487 #define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
488 #define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
489 #define IOMUXC_GPR1_DPI_OFF BIT(24)
490 #define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
491 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
492 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
493 #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
494 #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
495 #define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
496 #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
497 #define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
498 #define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
499 #define IOMUXC_GPR1_PCIE_INT BIT(14)
500 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
501 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
502 #define IOMUXC_GPR1_GINT BIT(12)
503 #define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
504 #define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
505 #define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
506 #define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
507 #define IOMUXC_GPR1_ACT_CS3 BIT(9)
508 #define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
509 #define IOMUXC_GPR1_ACT_CS2 BIT(6)
510 #define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
511 #define IOMUXC_GPR1_ACT_CS1 BIT(3)
512 #define IOMUXC_GPR1_ADDRS0_OFFSET (1)
513 #define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
514 #define IOMUXC_GPR1_ACT_CS0 BIT(0)
517 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
518 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
519 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
520 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
521 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
522 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
523 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
524 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
525 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
526 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
527 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
528 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
529 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
530 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
531 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
532 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
533 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
534 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
535 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
536 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
537 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
538 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
539 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
540 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
541 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
542 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
543 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
544 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
546 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
547 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
548 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
549 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
551 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
552 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
554 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
555 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
557 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
558 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
560 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
561 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
563 /* gpr12 bitfields */
564 #define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
565 #define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
566 #define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
567 #define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
568 #define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
569 #define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
570 #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
573 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
592 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
593 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
594 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
595 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
597 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
598 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
599 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
600 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
601 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
602 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
604 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
605 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
606 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
607 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
609 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
610 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
611 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
612 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
614 #define IOMUXC_GPR2_BITMAP_SPWG 0
615 #define IOMUXC_GPR2_BITMAP_JEIDA 1
617 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
618 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
619 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
620 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
622 #define IOMUXC_GPR2_DATA_WIDTH_18 0
623 #define IOMUXC_GPR2_DATA_WIDTH_24 1
625 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
626 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
627 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
628 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
630 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
631 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
632 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
633 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
635 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
636 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
637 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
638 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
640 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
641 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
643 #define IOMUXC_GPR2_MODE_DISABLED 0
644 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
645 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3
647 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
648 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
649 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
650 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
651 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
653 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
654 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
655 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
656 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
657 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
659 /* ECSPI registers */
672 * CSPI register definitions
675 #define MXC_CSPICTRL_EN (1 << 0)
676 #define MXC_CSPICTRL_MODE (1 << 1)
677 #define MXC_CSPICTRL_XCH (1 << 2)
678 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
679 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
680 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
681 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
682 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
683 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
684 #define MXC_CSPICTRL_MAXBITS 0xfff
685 #define MXC_CSPICTRL_TC (1 << 7)
686 #define MXC_CSPICTRL_RXOVF (1 << 6)
687 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
688 #define MAX_SPI_BYTES 32
689 #define SPI_MAX_NUM 4
691 /* Bit position inside CTRL register to be associated with SS */
692 #define MXC_CSPICTRL_CHAN 18
694 /* Bit position inside CON register to be associated with SS */
695 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
696 #define MXC_CSPICON_POL 4 /* SCLK polarity */
697 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
698 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
699 #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
700 defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
701 #define MXC_SPI_BASE_ADDRESSES \
707 #define MXC_SPI_BASE_ADDRESSES \
747 struct fuse_bank0_regs {
766 struct fuse_bank1_regs {
785 struct fuse_bank4_regs {
794 u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
814 u32 pll_sys; /* 0x000 */
815 u32 pll_sys_set; /* 0x004 */
816 u32 pll_sys_clr; /* 0x008 */
817 u32 pll_sys_tog; /* 0x00c */
818 u32 usb1_pll_480_ctrl; /* 0x010 */
819 u32 usb1_pll_480_ctrl_set; /* 0x014 */
820 u32 usb1_pll_480_ctrl_clr; /* 0x018 */
821 u32 usb1_pll_480_ctrl_tog; /* 0x01c */
822 u32 usb2_pll_480_ctrl; /* 0x020 */
823 u32 usb2_pll_480_ctrl_set; /* 0x024 */
824 u32 usb2_pll_480_ctrl_clr; /* 0x028 */
825 u32 usb2_pll_480_ctrl_tog; /* 0x02c */
826 u32 pll_528; /* 0x030 */
827 u32 pll_528_set; /* 0x034 */
828 u32 pll_528_clr; /* 0x038 */
829 u32 pll_528_tog; /* 0x03c */
830 u32 pll_528_ss; /* 0x040 */
832 u32 pll_528_num; /* 0x050 */
834 u32 pll_528_denom; /* 0x060 */
836 u32 pll_audio; /* 0x070 */
837 u32 pll_audio_set; /* 0x074 */
838 u32 pll_audio_clr; /* 0x078 */
839 u32 pll_audio_tog; /* 0x07c */
840 u32 pll_audio_num; /* 0x080 */
842 u32 pll_audio_denom; /* 0x090 */
844 u32 pll_video; /* 0x0a0 */
845 u32 pll_video_set; /* 0x0a4 */
846 u32 pll_video_clr; /* 0x0a8 */
847 u32 pll_video_tog; /* 0x0ac */
848 u32 pll_video_num; /* 0x0b0 */
850 u32 pll_video_denom; /* 0x0c0 */
852 u32 pll_mlb; /* 0x0d0 */
853 u32 pll_mlb_set; /* 0x0d4 */
854 u32 pll_mlb_clr; /* 0x0d8 */
855 u32 pll_mlb_tog; /* 0x0dc */
856 u32 pll_enet; /* 0x0e0 */
857 u32 pll_enet_set; /* 0x0e4 */
858 u32 pll_enet_clr; /* 0x0e8 */
859 u32 pll_enet_tog; /* 0x0ec */
860 u32 pfd_480; /* 0x0f0 */
861 u32 pfd_480_set; /* 0x0f4 */
862 u32 pfd_480_clr; /* 0x0f8 */
863 u32 pfd_480_tog; /* 0x0fc */
864 u32 pfd_528; /* 0x100 */
865 u32 pfd_528_set; /* 0x104 */
866 u32 pfd_528_clr; /* 0x108 */
867 u32 pfd_528_tog; /* 0x10c */
868 u32 reg_1p1; /* 0x110 */
869 u32 reg_1p1_set; /* 0x114 */
870 u32 reg_1p1_clr; /* 0x118 */
871 u32 reg_1p1_tog; /* 0x11c */
872 u32 reg_3p0; /* 0x120 */
873 u32 reg_3p0_set; /* 0x124 */
874 u32 reg_3p0_clr; /* 0x128 */
875 u32 reg_3p0_tog; /* 0x12c */
876 u32 reg_2p5; /* 0x130 */
877 u32 reg_2p5_set; /* 0x134 */
878 u32 reg_2p5_clr; /* 0x138 */
879 u32 reg_2p5_tog; /* 0x13c */
880 u32 reg_core; /* 0x140 */
881 u32 reg_core_set; /* 0x144 */
882 u32 reg_core_clr; /* 0x148 */
883 u32 reg_core_tog; /* 0x14c */
884 u32 ana_misc0; /* 0x150 */
885 u32 ana_misc0_set; /* 0x154 */
886 u32 ana_misc0_clr; /* 0x158 */
887 u32 ana_misc0_tog; /* 0x15c */
888 u32 ana_misc1; /* 0x160 */
889 u32 ana_misc1_set; /* 0x164 */
890 u32 ana_misc1_clr; /* 0x168 */
891 u32 ana_misc1_tog; /* 0x16c */
892 u32 ana_misc2; /* 0x170 */
893 u32 ana_misc2_set; /* 0x174 */
894 u32 ana_misc2_clr; /* 0x178 */
895 u32 ana_misc2_tog; /* 0x17c */
896 u32 tempsense0; /* 0x180 */
897 u32 tempsense0_set; /* 0x184 */
898 u32 tempsense0_clr; /* 0x188 */
899 u32 tempsense0_tog; /* 0x18c */
900 u32 tempsense1; /* 0x190 */
901 u32 tempsense1_set; /* 0x194 */
902 u32 tempsense1_clr; /* 0x198 */
903 u32 tempsense1_tog; /* 0x19c */
904 u32 usb1_vbus_detect; /* 0x1a0 */
905 u32 usb1_vbus_detect_set; /* 0x1a4 */
906 u32 usb1_vbus_detect_clr; /* 0x1a8 */
907 u32 usb1_vbus_detect_tog; /* 0x1ac */
908 u32 usb1_chrg_detect; /* 0x1b0 */
909 u32 usb1_chrg_detect_set; /* 0x1b4 */
910 u32 usb1_chrg_detect_clr; /* 0x1b8 */
911 u32 usb1_chrg_detect_tog; /* 0x1bc */
912 u32 usb1_vbus_det_stat; /* 0x1c0 */
913 u32 usb1_vbus_det_stat_set; /* 0x1c4 */
914 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
915 u32 usb1_vbus_det_stat_tog; /* 0x1cc */
916 u32 usb1_chrg_det_stat; /* 0x1d0 */
917 u32 usb1_chrg_det_stat_set; /* 0x1d4 */
918 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
919 u32 usb1_chrg_det_stat_tog; /* 0x1dc */
920 u32 usb1_loopback; /* 0x1e0 */
921 u32 usb1_loopback_set; /* 0x1e4 */
922 u32 usb1_loopback_clr; /* 0x1e8 */
923 u32 usb1_loopback_tog; /* 0x1ec */
924 u32 usb1_misc; /* 0x1f0 */
925 u32 usb1_misc_set; /* 0x1f4 */
926 u32 usb1_misc_clr; /* 0x1f8 */
927 u32 usb1_misc_tog; /* 0x1fc */
928 u32 usb2_vbus_detect; /* 0x200 */
929 u32 usb2_vbus_detect_set; /* 0x204 */
930 u32 usb2_vbus_detect_clr; /* 0x208 */
931 u32 usb2_vbus_detect_tog; /* 0x20c */
932 u32 usb2_chrg_detect; /* 0x210 */
933 u32 usb2_chrg_detect_set; /* 0x214 */
934 u32 usb2_chrg_detect_clr; /* 0x218 */
935 u32 usb2_chrg_detect_tog; /* 0x21c */
936 u32 usb2_vbus_det_stat; /* 0x220 */
937 u32 usb2_vbus_det_stat_set; /* 0x224 */
938 u32 usb2_vbus_det_stat_clr; /* 0x228 */
939 u32 usb2_vbus_det_stat_tog; /* 0x22c */
940 u32 usb2_chrg_det_stat; /* 0x230 */
941 u32 usb2_chrg_det_stat_set; /* 0x234 */
942 u32 usb2_chrg_det_stat_clr; /* 0x238 */
943 u32 usb2_chrg_det_stat_tog; /* 0x23c */
944 u32 usb2_loopback; /* 0x240 */
945 u32 usb2_loopback_set; /* 0x244 */
946 u32 usb2_loopback_clr; /* 0x248 */
947 u32 usb2_loopback_tog; /* 0x24c */
948 u32 usb2_misc; /* 0x250 */
949 u32 usb2_misc_set; /* 0x254 */
950 u32 usb2_misc_clr; /* 0x258 */
951 u32 usb2_misc_tog; /* 0x25c */
952 u32 digprog; /* 0x260 */
954 u32 digprog_sololite; /* 0x280 */
957 #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
958 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
959 #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
960 #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
961 #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
962 #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
965 u16 wcr; /* Control */
966 u16 wsr; /* Service */
967 u16 wrsr; /* Reset Status */
968 u16 wicr; /* Interrupt Control */
969 u16 wmcr; /* Miscellaneous Control */
972 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
973 #define PWMCR_DOZEEN (1 << 24)
974 #define PWMCR_WAITEN (1 << 23)
975 #define PWMCR_DBGEN (1 << 22)
976 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
977 #define PWMCR_CLKSRC_IPG (1 << 16)
978 #define PWMCR_EN (1 << 0)
988 #endif /* __ASSEMBLER__*/
989 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */