2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
12 #define CONFIG_SYS_CACHELINE_SIZE 32
14 #define ROMCP_ARB_BASE_ADDR 0x00000000
15 #define ROMCP_ARB_END_ADDR 0x000FFFFF
18 #define GPU_2D_ARB_BASE_ADDR 0x02200000
19 #define GPU_2D_ARB_END_ADDR 0x02203FFF
20 #define OPENVG_ARB_BASE_ADDR 0x02204000
21 #define OPENVG_ARB_END_ADDR 0x02207FFF
22 #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
23 #define CAAM_ARB_BASE_ADDR 0x00100000
24 #define CAAM_ARB_END_ADDR 0x00107FFF
25 #define GPU_ARB_BASE_ADDR 0x01800000
26 #define GPU_ARB_END_ADDR 0x01803FFF
27 #define APBH_DMA_ARB_BASE_ADDR 0x01804000
28 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
29 #define M4_BOOTROM_BASE_ADDR 0x007F8000
32 #define CAAM_ARB_BASE_ADDR 0x00100000
33 #define CAAM_ARB_END_ADDR 0x00103FFF
34 #define APBH_DMA_ARB_BASE_ADDR 0x00110000
35 #define APBH_DMA_ARB_END_ADDR 0x00117FFF
36 #define HDMI_ARB_BASE_ADDR 0x00120000
37 #define HDMI_ARB_END_ADDR 0x00128FFF
38 #define GPU_3D_ARB_BASE_ADDR 0x00130000
39 #define GPU_3D_ARB_END_ADDR 0x00133FFF
40 #define GPU_2D_ARB_BASE_ADDR 0x00134000
41 #define GPU_2D_ARB_END_ADDR 0x00137FFF
42 #define DTCP_ARB_BASE_ADDR 0x00138000
43 #define DTCP_ARB_END_ADDR 0x0013BFFF
44 #endif /* CONFIG_MX6SL */
46 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
47 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
48 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
50 /* GPV - PL301 configuration ports */
51 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
52 #define GPV2_BASE_ADDR 0x00D00000
54 #define GPV2_BASE_ADDR 0x00200000
57 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
58 #define GPV3_BASE_ADDR 0x00E00000
59 #define GPV4_BASE_ADDR 0x00F00000
60 #define GPV5_BASE_ADDR 0x01000000
61 #define GPV6_BASE_ADDR 0x01100000
62 #define PCIE_ARB_BASE_ADDR 0x08000000
63 #define PCIE_ARB_END_ADDR 0x08FFFFFF
66 #define GPV3_BASE_ADDR 0x00300000
67 #define GPV4_BASE_ADDR 0x00800000
68 #define PCIE_ARB_BASE_ADDR 0x01000000
69 #define PCIE_ARB_END_ADDR 0x01FFFFFF
72 #define IRAM_BASE_ADDR 0x00900000
73 #define SCU_BASE_ADDR 0x00A00000
74 #define IC_INTERFACES_BASE_ADDR 0x00A00100
75 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
76 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
77 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
78 #define L2_PL310_BASE 0x00A02000
79 #define GPV0_BASE_ADDR 0x00B00000
80 #define GPV1_BASE_ADDR 0x00C00000
82 #define AIPS1_ARB_BASE_ADDR 0x02000000
83 #define AIPS1_ARB_END_ADDR 0x020FFFFF
84 #define AIPS2_ARB_BASE_ADDR 0x02100000
85 #define AIPS2_ARB_END_ADDR 0x021FFFFF
86 /* AIPS3 only on i.MX6SX */
87 #define AIPS3_ARB_BASE_ADDR 0x02200000
88 #define AIPS3_ARB_END_ADDR 0x022FFFFF
90 #define WEIM_ARB_BASE_ADDR 0x50000000
91 #define WEIM_ARB_END_ADDR 0x57FFFFFF
92 #define QSPI0_AMBA_BASE 0x60000000
93 #define QSPI0_AMBA_END 0x6FFFFFFF
94 #define QSPI1_AMBA_BASE 0x70000000
95 #define QSPI1_AMBA_END 0x7FFFFFFF
96 #elif defined(CONFIG_MX6UL)
97 #define WEIM_ARB_BASE_ADDR 0x50000000
98 #define WEIM_ARB_END_ADDR 0x57FFFFFF
99 #define QSPI0_AMBA_BASE 0x60000000
100 #define QSPI0_AMBA_END 0x6FFFFFFF
102 #define SATA_ARB_BASE_ADDR 0x02200000
103 #define SATA_ARB_END_ADDR 0x02203FFF
104 #define OPENVG_ARB_BASE_ADDR 0x02204000
105 #define OPENVG_ARB_END_ADDR 0x02207FFF
106 #define HSI_ARB_BASE_ADDR 0x02208000
107 #define HSI_ARB_END_ADDR 0x0220BFFF
108 #define IPU1_ARB_BASE_ADDR 0x02400000
109 #define IPU1_ARB_END_ADDR 0x027FFFFF
110 #define IPU2_ARB_BASE_ADDR 0x02800000
111 #define IPU2_ARB_END_ADDR 0x02BFFFFF
112 #define WEIM_ARB_BASE_ADDR 0x08000000
113 #define WEIM_ARB_END_ADDR 0x0FFFFFFF
116 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
117 #define MMDC0_ARB_BASE_ADDR 0x80000000
118 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
119 #define MMDC1_ARB_BASE_ADDR 0xC0000000
120 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
122 #define MMDC0_ARB_BASE_ADDR 0x10000000
123 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
124 #define MMDC1_ARB_BASE_ADDR 0x80000000
125 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
129 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
130 #define IPU_SOC_OFFSET 0x00200000
133 /* Defines for Blocks connected via AIPS (SkyBlue) */
134 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
135 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
136 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
137 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
139 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
140 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
141 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
142 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
143 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
145 #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
146 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
147 #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
148 #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
149 #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
150 #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
151 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
152 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
155 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
157 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
158 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
159 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
160 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
161 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
162 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
166 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
167 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
169 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
171 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
172 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
173 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
174 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
175 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
176 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
177 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
178 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
179 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
180 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
181 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
182 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
183 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
184 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
185 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
186 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
187 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
188 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
189 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
190 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
191 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
192 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
193 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
194 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
195 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
196 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
197 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
198 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
200 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
201 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
202 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
204 #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
205 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
206 #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
207 #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
208 #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
209 #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
211 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
212 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
213 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
216 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
217 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
218 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
219 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
221 #define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR
222 #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000)
224 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
225 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
227 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
229 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
231 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
234 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
235 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
236 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
237 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
238 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
239 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
240 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
241 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
242 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
244 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
246 #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
249 #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
252 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
254 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
255 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
256 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
257 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
258 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
260 #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
262 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
264 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
266 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
267 #elif defined(CONFIG_MX6SX)
268 #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
269 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
270 #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
271 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
272 #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
274 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
275 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
276 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
277 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
279 #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
280 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
281 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
282 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
283 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
284 #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
285 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
286 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
289 #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
290 #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
291 #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
292 #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
293 #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
294 #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
295 #define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
296 #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
297 #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
298 #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
299 #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
300 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
301 #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
302 #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
303 #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
304 #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
305 #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
306 #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
307 #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
308 #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
309 #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
310 #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
311 #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
312 #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
314 #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
316 /* only for i.MX6SX/UL */
317 #define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
318 MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
320 #define CHIP_REV_1_0 0x10
321 #define CHIP_REV_1_2 0x12
322 #define CHIP_REV_1_5 0x15
323 #define CHIP_REV_2_0 0x20
324 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
325 #define IRAM_SIZE 0x00040000
327 #define IRAM_SIZE 0x00020000
329 #define FEC_QUIRK_ENET_MAC
331 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
332 #include <asm/types.h>
334 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
336 #define SRC_SCR_CORE_1_RESET_OFFSET 14
337 #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
338 #define SRC_SCR_CORE_2_RESET_OFFSET 15
339 #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
340 #define SRC_SCR_CORE_3_RESET_OFFSET 16
341 #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
342 #define SRC_SCR_CORE_1_ENABLE_OFFSET 22
343 #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
344 #define SRC_SCR_CORE_2_ENABLE_OFFSET 23
345 #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
346 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24
347 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
386 /* System Reset Controller (SRC) */
408 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
409 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
410 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
411 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
414 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
415 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
416 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
417 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
418 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
419 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
420 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
421 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
422 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
423 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
424 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
425 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
426 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
427 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
428 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
429 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
430 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
431 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
432 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
433 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
434 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
435 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
436 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
437 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
438 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
439 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
440 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
441 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
443 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
444 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
445 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
446 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
448 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
449 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
451 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
452 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
454 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
455 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
457 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
458 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
462 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
481 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
482 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
483 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
484 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
486 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
487 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
488 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
489 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
490 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
491 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
493 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
494 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
495 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
496 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
498 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
499 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
500 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
501 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
503 #define IOMUXC_GPR2_BITMAP_SPWG 0
504 #define IOMUXC_GPR2_BITMAP_JEIDA 1
506 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
507 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
508 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
509 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
511 #define IOMUXC_GPR2_DATA_WIDTH_18 0
512 #define IOMUXC_GPR2_DATA_WIDTH_24 1
514 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
515 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
516 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
517 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
519 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
520 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
521 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
522 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
524 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
525 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
526 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
527 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
529 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
530 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
532 #define IOMUXC_GPR2_MODE_DISABLED 0
533 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
534 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3
536 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
537 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
538 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
539 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
540 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
542 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
543 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
544 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
545 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
546 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
548 /* ECSPI registers */
561 * CSPI register definitions
564 #define MXC_CSPICTRL_EN (1 << 0)
565 #define MXC_CSPICTRL_MODE (1 << 1)
566 #define MXC_CSPICTRL_XCH (1 << 2)
567 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
568 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
569 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
570 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
571 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
572 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
573 #define MXC_CSPICTRL_MAXBITS 0xfff
574 #define MXC_CSPICTRL_TC (1 << 7)
575 #define MXC_CSPICTRL_RXOVF (1 << 6)
576 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
577 #define MAX_SPI_BYTES 32
578 #define SPI_MAX_NUM 4
580 /* Bit position inside CTRL register to be associated with SS */
581 #define MXC_CSPICTRL_CHAN 18
583 /* Bit position inside CON register to be associated with SS */
584 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
585 #define MXC_CSPICON_POL 4 /* SCLK polarity */
586 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
587 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
588 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
589 #define MXC_SPI_BASE_ADDRESSES \
595 #define MXC_SPI_BASE_ADDRESSES \
634 struct fuse_bank0_regs {
653 struct fuse_bank1_regs {
672 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
673 struct fuse_bank4_regs {
690 struct fuse_bank4_regs {
718 u32 pll_sys; /* 0x000 */
719 u32 pll_sys_set; /* 0x004 */
720 u32 pll_sys_clr; /* 0x008 */
721 u32 pll_sys_tog; /* 0x00c */
722 u32 usb1_pll_480_ctrl; /* 0x010 */
723 u32 usb1_pll_480_ctrl_set; /* 0x014 */
724 u32 usb1_pll_480_ctrl_clr; /* 0x018 */
725 u32 usb1_pll_480_ctrl_tog; /* 0x01c */
726 u32 usb2_pll_480_ctrl; /* 0x020 */
727 u32 usb2_pll_480_ctrl_set; /* 0x024 */
728 u32 usb2_pll_480_ctrl_clr; /* 0x028 */
729 u32 usb2_pll_480_ctrl_tog; /* 0x02c */
730 u32 pll_528; /* 0x030 */
731 u32 pll_528_set; /* 0x034 */
732 u32 pll_528_clr; /* 0x038 */
733 u32 pll_528_tog; /* 0x03c */
734 u32 pll_528_ss; /* 0x040 */
736 u32 pll_528_num; /* 0x050 */
738 u32 pll_528_denom; /* 0x060 */
740 u32 pll_audio; /* 0x070 */
741 u32 pll_audio_set; /* 0x074 */
742 u32 pll_audio_clr; /* 0x078 */
743 u32 pll_audio_tog; /* 0x07c */
744 u32 pll_audio_num; /* 0x080 */
746 u32 pll_audio_denom; /* 0x090 */
748 u32 pll_video; /* 0x0a0 */
749 u32 pll_video_set; /* 0x0a4 */
750 u32 pll_video_clr; /* 0x0a8 */
751 u32 pll_video_tog; /* 0x0ac */
752 u32 pll_video_num; /* 0x0b0 */
754 u32 pll_video_denom; /* 0x0c0 */
756 u32 pll_mlb; /* 0x0d0 */
757 u32 pll_mlb_set; /* 0x0d4 */
758 u32 pll_mlb_clr; /* 0x0d8 */
759 u32 pll_mlb_tog; /* 0x0dc */
760 u32 pll_enet; /* 0x0e0 */
761 u32 pll_enet_set; /* 0x0e4 */
762 u32 pll_enet_clr; /* 0x0e8 */
763 u32 pll_enet_tog; /* 0x0ec */
764 u32 pfd_480; /* 0x0f0 */
765 u32 pfd_480_set; /* 0x0f4 */
766 u32 pfd_480_clr; /* 0x0f8 */
767 u32 pfd_480_tog; /* 0x0fc */
768 u32 pfd_528; /* 0x100 */
769 u32 pfd_528_set; /* 0x104 */
770 u32 pfd_528_clr; /* 0x108 */
771 u32 pfd_528_tog; /* 0x10c */
772 u32 reg_1p1; /* 0x110 */
773 u32 reg_1p1_set; /* 0x114 */
774 u32 reg_1p1_clr; /* 0x118 */
775 u32 reg_1p1_tog; /* 0x11c */
776 u32 reg_3p0; /* 0x120 */
777 u32 reg_3p0_set; /* 0x124 */
778 u32 reg_3p0_clr; /* 0x128 */
779 u32 reg_3p0_tog; /* 0x12c */
780 u32 reg_2p5; /* 0x130 */
781 u32 reg_2p5_set; /* 0x134 */
782 u32 reg_2p5_clr; /* 0x138 */
783 u32 reg_2p5_tog; /* 0x13c */
784 u32 reg_core; /* 0x140 */
785 u32 reg_core_set; /* 0x144 */
786 u32 reg_core_clr; /* 0x148 */
787 u32 reg_core_tog; /* 0x14c */
788 u32 ana_misc0; /* 0x150 */
789 u32 ana_misc0_set; /* 0x154 */
790 u32 ana_misc0_clr; /* 0x158 */
791 u32 ana_misc0_tog; /* 0x15c */
792 u32 ana_misc1; /* 0x160 */
793 u32 ana_misc1_set; /* 0x164 */
794 u32 ana_misc1_clr; /* 0x168 */
795 u32 ana_misc1_tog; /* 0x16c */
796 u32 ana_misc2; /* 0x170 */
797 u32 ana_misc2_set; /* 0x174 */
798 u32 ana_misc2_clr; /* 0x178 */
799 u32 ana_misc2_tog; /* 0x17c */
800 u32 tempsense0; /* 0x180 */
801 u32 tempsense0_set; /* 0x184 */
802 u32 tempsense0_clr; /* 0x188 */
803 u32 tempsense0_tog; /* 0x18c */
804 u32 tempsense1; /* 0x190 */
805 u32 tempsense1_set; /* 0x194 */
806 u32 tempsense1_clr; /* 0x198 */
807 u32 tempsense1_tog; /* 0x19c */
808 u32 usb1_vbus_detect; /* 0x1a0 */
809 u32 usb1_vbus_detect_set; /* 0x1a4 */
810 u32 usb1_vbus_detect_clr; /* 0x1a8 */
811 u32 usb1_vbus_detect_tog; /* 0x1ac */
812 u32 usb1_chrg_detect; /* 0x1b0 */
813 u32 usb1_chrg_detect_set; /* 0x1b4 */
814 u32 usb1_chrg_detect_clr; /* 0x1b8 */
815 u32 usb1_chrg_detect_tog; /* 0x1bc */
816 u32 usb1_vbus_det_stat; /* 0x1c0 */
817 u32 usb1_vbus_det_stat_set; /* 0x1c4 */
818 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
819 u32 usb1_vbus_det_stat_tog; /* 0x1cc */
820 u32 usb1_chrg_det_stat; /* 0x1d0 */
821 u32 usb1_chrg_det_stat_set; /* 0x1d4 */
822 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
823 u32 usb1_chrg_det_stat_tog; /* 0x1dc */
824 u32 usb1_loopback; /* 0x1e0 */
825 u32 usb1_loopback_set; /* 0x1e4 */
826 u32 usb1_loopback_clr; /* 0x1e8 */
827 u32 usb1_loopback_tog; /* 0x1ec */
828 u32 usb1_misc; /* 0x1f0 */
829 u32 usb1_misc_set; /* 0x1f4 */
830 u32 usb1_misc_clr; /* 0x1f8 */
831 u32 usb1_misc_tog; /* 0x1fc */
832 u32 usb2_vbus_detect; /* 0x200 */
833 u32 usb2_vbus_detect_set; /* 0x204 */
834 u32 usb2_vbus_detect_clr; /* 0x208 */
835 u32 usb2_vbus_detect_tog; /* 0x20c */
836 u32 usb2_chrg_detect; /* 0x210 */
837 u32 usb2_chrg_detect_set; /* 0x214 */
838 u32 usb2_chrg_detect_clr; /* 0x218 */
839 u32 usb2_chrg_detect_tog; /* 0x21c */
840 u32 usb2_vbus_det_stat; /* 0x220 */
841 u32 usb2_vbus_det_stat_set; /* 0x224 */
842 u32 usb2_vbus_det_stat_clr; /* 0x228 */
843 u32 usb2_vbus_det_stat_tog; /* 0x22c */
844 u32 usb2_chrg_det_stat; /* 0x230 */
845 u32 usb2_chrg_det_stat_set; /* 0x234 */
846 u32 usb2_chrg_det_stat_clr; /* 0x238 */
847 u32 usb2_chrg_det_stat_tog; /* 0x23c */
848 u32 usb2_loopback; /* 0x240 */
849 u32 usb2_loopback_set; /* 0x244 */
850 u32 usb2_loopback_clr; /* 0x248 */
851 u32 usb2_loopback_tog; /* 0x24c */
852 u32 usb2_misc; /* 0x250 */
853 u32 usb2_misc_set; /* 0x254 */
854 u32 usb2_misc_clr; /* 0x258 */
855 u32 usb2_misc_tog; /* 0x25c */
856 u32 digprog; /* 0x260 */
858 u32 digprog_sololite; /* 0x280 */
861 #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
862 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
863 #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
864 #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
865 #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
866 #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
869 u16 wcr; /* Control */
870 u16 wsr; /* Service */
871 u16 wrsr; /* Reset Status */
872 u16 wicr; /* Interrupt Control */
873 u16 wmcr; /* Miscellaneous Control */
876 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
877 #define PWMCR_DOZEEN (1 << 24)
878 #define PWMCR_WAITEN (1 << 23)
879 #define PWMCR_DBGEN (1 << 22)
880 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
881 #define PWMCR_CLKSRC_IPG (1 << 16)
882 #define PWMCR_EN (1 << 0)
892 #endif /* __ASSEMBLER__*/
893 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */