2 * Copyright (C) 2013 Boundary Devices Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __ASM_ARCH_MX6_DDR_H__
7 #define __ASM_ARCH_MX6_DDR_H__
9 #ifndef CONFIG_SPL_BUILD
13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
14 #include "mx6dl-ddr.h"
17 #include "mx6sx-ddr.h"
20 #include "mx6ul-ddr.h"
23 #include "mx6sl-ddr.h"
25 #error "Please select cpu"
26 #endif /* CONFIG_MX6SL */
27 #endif /* CONFIG_MX6UL */
28 #endif /* CONFIG_MX6SX */
29 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
30 #endif /* CONFIG_MX6Q */
38 /* MMDC P0/P1 Registers */
125 #define MX6SL_IOM_DDR_BASE 0x020e0300
126 struct mx6sl_iomux_ddr_regs {
151 #define MX6SL_IOM_GRP_BASE 0x020e0500
152 struct mx6sl_iomux_grp_regs {
168 #define MX6UL_IOM_DDR_BASE 0x020e0200
169 struct mx6ul_iomux_ddr_regs {
191 #define MX6UL_IOM_GRP_BASE 0x020e0400
192 struct mx6ul_iomux_grp_regs {
206 #define MX6SX_IOM_DDR_BASE 0x020e0200
207 struct mx6sx_iomux_ddr_regs {
232 #define MX6SX_IOM_GRP_BASE 0x020e0500
233 struct mx6sx_iomux_grp_regs {
250 * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
252 #define MX6DQ_IOM_DDR_BASE 0x020e0500
253 struct mx6dq_iomux_ddr_regs {
287 #define MX6DQ_IOM_GRP_BASE 0x020e0700
288 struct mx6dq_iomux_grp_regs {
310 #define MX6SDL_IOM_DDR_BASE 0x020e0400
311 struct mx6sdl_iomux_ddr_regs {
343 #define MX6SDL_IOM_GRP_BASE 0x020e0700
344 struct mx6sdl_iomux_grp_regs {
365 /* Device Information: Varies per DDR3 part number and speed grade */
366 struct mx6_ddr3_cfg {
367 u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
368 u8 density; /* chip density (Gb) (1,2,4,8) */
369 u8 width; /* bus width (bits) (4,8,16) */
370 u8 banks; /* number of banks */
371 u8 rowaddr; /* row address bits (11-16)*/
372 u8 coladdr; /* col address bits (9-12) */
373 u8 pagesz; /* page size (K) (1-2) */
374 u16 trcd; /* tRCD=tRP=CL (ns*100) */
375 u16 trcmin; /* tRC min (ns*100) */
376 u16 trasmin; /* tRAS min (ns*100) */
377 u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
380 /* Device Information: Varies per LPDDR2 part number and speed grade */
381 struct mx6_lpddr2_cfg {
382 u16 mem_speed; /* ie 800 for LPDDR2-800 */
383 u8 density; /* chip density (Gb) (1,2,4,8) */
384 u8 width; /* bus width (bits) (4,8,16) */
385 u8 banks; /* number of banks */
386 u8 rowaddr; /* row address bits (11-16)*/
387 u8 coladdr; /* col address bits (9-12) */
391 u16 trcmin; /* tRC min (ns*100) */
392 u16 trasmin; /* tRAS min (ns*100) */
395 /* System Information: Varies per board design, layout, and term choices */
396 struct mx6_ddr_sysinfo {
397 u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
398 u8 cs_density; /* density per chip select (Gb) */
399 u8 ncs; /* number chip selects used (1|2) */
400 char cs1_mirror;/* enable address mirror (0|1) */
401 char bi_on; /* Bank interleaving enable */
402 u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
403 u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
404 u8 ralat; /* Read Additional Latency (0-7) */
405 u8 walat; /* Write Additional Latency (0-3) */
406 u8 mif3_mode; /* Command prediction working mode */
407 u8 rst_to_cke; /* Time from SDE enable to CKE rise */
408 u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
409 u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
410 u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */
411 u8 refsel; /* REF_SEL field of register MDREF */
412 u8 refr; /* REFR field of register MDREF */
416 * Board specific calibration:
417 * This includes write leveling calibration values as well as DQS gating
418 * and read/write delays. These values are board/layout/device specific.
419 * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
420 * (DOC-96412) to determine these values over a range of boards and
423 struct mx6_mmdc_calibration {
424 /* write leveling calibration */
429 /* read DQS gating */
440 /* lpddr2 zq hw calibration */
444 /* configure iomux (pinctl/padctl) */
445 void mx6dq_dram_iocfg(unsigned width,
446 const struct mx6dq_iomux_ddr_regs *,
447 const struct mx6dq_iomux_grp_regs *);
448 void mx6sdl_dram_iocfg(unsigned width,
449 const struct mx6sdl_iomux_ddr_regs *,
450 const struct mx6sdl_iomux_grp_regs *);
451 void mx6sx_dram_iocfg(unsigned width,
452 const struct mx6sx_iomux_ddr_regs *,
453 const struct mx6sx_iomux_grp_regs *);
454 void mx6ul_dram_iocfg(unsigned width,
455 const struct mx6ul_iomux_ddr_regs *,
456 const struct mx6ul_iomux_grp_regs *);
457 void mx6sl_dram_iocfg(unsigned width,
458 const struct mx6sl_iomux_ddr_regs *,
459 const struct mx6sl_iomux_grp_regs *);
461 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
462 int mmdc_do_write_level_calibration(void);
463 int mmdc_do_dqs_calibration(void);
466 /* configure mx6 mmdc registers */
467 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
468 const struct mx6_mmdc_calibration *,
471 #endif /* CONFIG_SPL_BUILD */
473 #define MX6_MMDC_P0_MDCTL 0x021b0000
474 #define MX6_MMDC_P0_MDPDC 0x021b0004
475 #define MX6_MMDC_P0_MDOTC 0x021b0008
476 #define MX6_MMDC_P0_MDCFG0 0x021b000c
477 #define MX6_MMDC_P0_MDCFG1 0x021b0010
478 #define MX6_MMDC_P0_MDCFG2 0x021b0014
479 #define MX6_MMDC_P0_MDMISC 0x021b0018
480 #define MX6_MMDC_P0_MDSCR 0x021b001c
481 #define MX6_MMDC_P0_MDREF 0x021b0020
482 #define MX6_MMDC_P0_MDRWD 0x021b002c
483 #define MX6_MMDC_P0_MDOR 0x021b0030
484 #define MX6_MMDC_P0_MDASP 0x021b0040
485 #define MX6_MMDC_P0_MAPSR 0x021b0404
486 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
487 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
488 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
489 #define MX6_MMDC_P0_MPODTCTRL 0x021b0818
490 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
491 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
492 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
493 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
494 #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
495 #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
496 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
497 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
498 #define MX6_MMDC_P0_MPMUR0 0x021b08b8
500 #define MX6_MMDC_P1_MDCTL 0x021b4000
501 #define MX6_MMDC_P1_MDPDC 0x021b4004
502 #define MX6_MMDC_P1_MDOTC 0x021b4008
503 #define MX6_MMDC_P1_MDCFG0 0x021b400c
504 #define MX6_MMDC_P1_MDCFG1 0x021b4010
505 #define MX6_MMDC_P1_MDCFG2 0x021b4014
506 #define MX6_MMDC_P1_MDMISC 0x021b4018
507 #define MX6_MMDC_P1_MDSCR 0x021b401c
508 #define MX6_MMDC_P1_MDREF 0x021b4020
509 #define MX6_MMDC_P1_MDRWD 0x021b402c
510 #define MX6_MMDC_P1_MDOR 0x021b4030
511 #define MX6_MMDC_P1_MDASP 0x021b4040
512 #define MX6_MMDC_P1_MAPSR 0x021b4404
513 #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
514 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
515 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
516 #define MX6_MMDC_P1_MPODTCTRL 0x021b4818
517 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
518 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
519 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
520 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
521 #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
522 #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
523 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
524 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
525 #define MX6_MMDC_P1_MPMUR0 0x021b48b8
527 #endif /*__ASM_ARCH_MX6_DDR_H__ */