2 * Copyright (C) 2013 Boundary Devices Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __ASM_ARCH_MX6_DDR_H__
7 #define __ASM_ARCH_MX6_DDR_H__
9 #ifndef CONFIG_SPL_BUILD
13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
14 #include "mx6dl-ddr.h"
17 #include "mx6sx-ddr.h"
20 #include "mx6ul-ddr.h"
22 #error "Please select cpu"
23 #endif /* CONFIG_MX6UL */
24 #endif /* CONFIG_MX6SX */
25 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
26 #endif /* CONFIG_MX6Q */
29 /* MMDC P0/P1 Registers */
116 #define MX6UL_IOM_DDR_BASE 0x020e0200
117 struct mx6ul_iomux_ddr_regs {
139 #define MX6UL_IOM_GRP_BASE 0x020e0400
140 struct mx6ul_iomux_grp_regs {
154 #define MX6SX_IOM_DDR_BASE 0x020e0200
155 struct mx6sx_iomux_ddr_regs {
180 #define MX6SX_IOM_GRP_BASE 0x020e0500
181 struct mx6sx_iomux_grp_regs {
198 * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
200 #define MX6DQ_IOM_DDR_BASE 0x020e0500
201 struct mx6dq_iomux_ddr_regs {
235 #define MX6DQ_IOM_GRP_BASE 0x020e0700
236 struct mx6dq_iomux_grp_regs {
258 #define MX6SDL_IOM_DDR_BASE 0x020e0400
259 struct mx6sdl_iomux_ddr_regs {
291 #define MX6SDL_IOM_GRP_BASE 0x020e0700
292 struct mx6sdl_iomux_grp_regs {
313 /* Device Information: Varies per DDR3 part number and speed grade */
314 struct mx6_ddr3_cfg {
315 u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
316 u8 density; /* chip density (Gb) (1,2,4,8) */
317 u8 width; /* bus width (bits) (4,8,16) */
318 u8 banks; /* number of banks */
319 u8 rowaddr; /* row address bits (11-16)*/
320 u8 coladdr; /* col address bits (9-12) */
321 u8 pagesz; /* page size (K) (1-2) */
322 u16 trcd; /* tRCD=tRP=CL (ns*100) */
323 u16 trcmin; /* tRC min (ns*100) */
324 u16 trasmin; /* tRAS min (ns*100) */
325 u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
328 /* System Information: Varies per board design, layout, and term choices */
329 struct mx6_ddr_sysinfo {
330 u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
331 u8 cs_density; /* density per chip select (Gb) */
332 u8 ncs; /* number chip selects used (1|2) */
333 char cs1_mirror;/* enable address mirror (0|1) */
334 char bi_on; /* Bank interleaving enable */
335 u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
336 u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
337 u8 ralat; /* Read Additional Latency (0-7) */
338 u8 walat; /* Write Additional Latency (0-3) */
339 u8 mif3_mode; /* Command prediction working mode */
340 u8 rst_to_cke; /* Time from SDE enable to CKE rise */
341 u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
342 u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
346 * Board specific calibration:
347 * This includes write leveling calibration values as well as DQS gating
348 * and read/write delays. These values are board/layout/device specific.
349 * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
350 * (DOC-96412) to determine these values over a range of boards and
353 struct mx6_mmdc_calibration {
354 /* write leveling calibration */
359 /* read DQS gating */
372 /* configure iomux (pinctl/padctl) */
373 void mx6dq_dram_iocfg(unsigned width,
374 const struct mx6dq_iomux_ddr_regs *,
375 const struct mx6dq_iomux_grp_regs *);
376 void mx6sdl_dram_iocfg(unsigned width,
377 const struct mx6sdl_iomux_ddr_regs *,
378 const struct mx6sdl_iomux_grp_regs *);
379 void mx6sx_dram_iocfg(unsigned width,
380 const struct mx6sx_iomux_ddr_regs *,
381 const struct mx6sx_iomux_grp_regs *);
382 void mx6ul_dram_iocfg(unsigned width,
383 const struct mx6ul_iomux_ddr_regs *,
384 const struct mx6ul_iomux_grp_regs *);
386 /* configure mx6 mmdc registers */
387 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
388 const struct mx6_mmdc_calibration *,
389 const struct mx6_ddr3_cfg *);
391 #endif /* CONFIG_SPL_BUILD */
393 #define MX6_MMDC_P0_MDCTL 0x021b0000
394 #define MX6_MMDC_P0_MDPDC 0x021b0004
395 #define MX6_MMDC_P0_MDOTC 0x021b0008
396 #define MX6_MMDC_P0_MDCFG0 0x021b000c
397 #define MX6_MMDC_P0_MDCFG1 0x021b0010
398 #define MX6_MMDC_P0_MDCFG2 0x021b0014
399 #define MX6_MMDC_P0_MDMISC 0x021b0018
400 #define MX6_MMDC_P0_MDSCR 0x021b001c
401 #define MX6_MMDC_P0_MDREF 0x021b0020
402 #define MX6_MMDC_P0_MDRWD 0x021b002c
403 #define MX6_MMDC_P0_MDOR 0x021b0030
404 #define MX6_MMDC_P0_MDASP 0x021b0040
405 #define MX6_MMDC_P0_MAPSR 0x021b0404
406 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
407 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
408 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
409 #define MX6_MMDC_P0_MPODTCTRL 0x021b0818
410 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
411 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
412 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
413 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
414 #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
415 #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
416 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
417 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
418 #define MX6_MMDC_P0_MPMUR0 0x021b08b8
420 #define MX6_MMDC_P1_MDCTL 0x021b4000
421 #define MX6_MMDC_P1_MDPDC 0x021b4004
422 #define MX6_MMDC_P1_MDOTC 0x021b4008
423 #define MX6_MMDC_P1_MDCFG0 0x021b400c
424 #define MX6_MMDC_P1_MDCFG1 0x021b4010
425 #define MX6_MMDC_P1_MDCFG2 0x021b4014
426 #define MX6_MMDC_P1_MDMISC 0x021b4018
427 #define MX6_MMDC_P1_MDSCR 0x021b401c
428 #define MX6_MMDC_P1_MDREF 0x021b4020
429 #define MX6_MMDC_P1_MDRWD 0x021b402c
430 #define MX6_MMDC_P1_MDOR 0x021b4030
431 #define MX6_MMDC_P1_MDASP 0x021b4040
432 #define MX6_MMDC_P1_MAPSR 0x021b4404
433 #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
434 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
435 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
436 #define MX6_MMDC_P1_MPODTCTRL 0x021b4818
437 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
438 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
439 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
440 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
441 #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
442 #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
443 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
444 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
445 #define MX6_MMDC_P1_MPMUR0 0x021b48b8
447 #endif /*__ASM_ARCH_MX6_DDR_H__ */