2 * Copyright (C) 2013 Boundary Devices Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __ASM_ARCH_MX6_DDR_H__
7 #define __ASM_ARCH_MX6_DDR_H__
9 #ifndef CONFIG_SPL_BUILD
13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
14 #include "mx6dl-ddr.h"
17 #include "mx6sx-ddr.h"
19 #error "Please select cpu"
20 #endif /* CONFIG_MX6SX */
21 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
22 #endif /* CONFIG_MX6Q */
25 /* MMDC P0/P1 Registers */
65 #define MX6SX_IOM_DDR_BASE 0x020e0200
66 struct mx6sx_iomux_ddr_regs {
91 #define MX6SX_IOM_GRP_BASE 0x020e0500
92 struct mx6sx_iomux_grp_regs {
109 * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
111 #define MX6DQ_IOM_DDR_BASE 0x020e0500
112 struct mx6dq_iomux_ddr_regs {
146 #define MX6DQ_IOM_GRP_BASE 0x020e0700
147 struct mx6dq_iomux_grp_regs {
169 #define MX6SDL_IOM_DDR_BASE 0x020e0400
170 struct mx6sdl_iomux_ddr_regs {
202 #define MX6SDL_IOM_GRP_BASE 0x020e0700
203 struct mx6sdl_iomux_grp_regs {
224 /* Device Information: Varies per DDR3 part number and speed grade */
225 struct mx6_ddr3_cfg {
226 u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
227 u8 density; /* chip density (Gb) (1,2,4,8) */
228 u8 width; /* bus width (bits) (4,8,16) */
229 u8 banks; /* number of banks */
230 u8 rowaddr; /* row address bits (11-16)*/
231 u8 coladdr; /* col address bits (9-12) */
232 u8 pagesz; /* page size (K) (1-2) */
233 u16 trcd; /* tRCD=tRP=CL (ns*100) */
234 u16 trcmin; /* tRC min (ns*100) */
235 u16 trasmin; /* tRAS min (ns*100) */
236 u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
239 /* System Information: Varies per board design, layout, and term choices */
240 struct mx6_ddr_sysinfo {
241 u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
242 u8 cs_density; /* density per chip select (Gb) */
243 u8 ncs; /* number chip selects used (1|2) */
244 char cs1_mirror;/* enable address mirror (0|1) */
245 char bi_on; /* Bank interleaving enable */
246 u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
247 u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
248 u8 ralat; /* Read Additional Latency (0-7) */
249 u8 walat; /* Write Additional Latency (0-3) */
250 u8 mif3_mode; /* Command prediction working mode */
251 u8 rst_to_cke; /* Time from SDE enable to CKE rise */
252 u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
253 u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
257 * Board specific calibration:
258 * This includes write leveling calibration values as well as DQS gating
259 * and read/write delays. These values are board/layout/device specific.
260 * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
261 * (DOC-96412) to determine these values over a range of boards and
264 struct mx6_mmdc_calibration {
265 /* write leveling calibration */
270 /* read DQS gating */
283 /* configure iomux (pinctl/padctl) */
284 void mx6dq_dram_iocfg(unsigned width,
285 const struct mx6dq_iomux_ddr_regs *,
286 const struct mx6dq_iomux_grp_regs *);
287 void mx6sdl_dram_iocfg(unsigned width,
288 const struct mx6sdl_iomux_ddr_regs *,
289 const struct mx6sdl_iomux_grp_regs *);
290 void mx6sx_dram_iocfg(unsigned width,
291 const struct mx6sx_iomux_ddr_regs *,
292 const struct mx6sx_iomux_grp_regs *);
294 /* configure mx6 mmdc registers */
295 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
296 const struct mx6_mmdc_calibration *,
297 const struct mx6_ddr3_cfg *);
299 #endif /* CONFIG_SPL_BUILD */
301 #define MX6_MMDC_P0_MDCTL 0x021b0000
302 #define MX6_MMDC_P0_MDPDC 0x021b0004
303 #define MX6_MMDC_P0_MDOTC 0x021b0008
304 #define MX6_MMDC_P0_MDCFG0 0x021b000c
305 #define MX6_MMDC_P0_MDCFG1 0x021b0010
306 #define MX6_MMDC_P0_MDCFG2 0x021b0014
307 #define MX6_MMDC_P0_MDMISC 0x021b0018
308 #define MX6_MMDC_P0_MDSCR 0x021b001c
309 #define MX6_MMDC_P0_MDREF 0x021b0020
310 #define MX6_MMDC_P0_MDRWD 0x021b002c
311 #define MX6_MMDC_P0_MDOR 0x021b0030
312 #define MX6_MMDC_P0_MDASP 0x021b0040
313 #define MX6_MMDC_P0_MAPSR 0x021b0404
314 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
315 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
316 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
317 #define MX6_MMDC_P0_MPODTCTRL 0x021b0818
318 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
319 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
320 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
321 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
322 #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
323 #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
324 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
325 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
326 #define MX6_MMDC_P0_MPMUR0 0x021b08b8
328 #define MX6_MMDC_P1_MDCTL 0x021b4000
329 #define MX6_MMDC_P1_MDPDC 0x021b4004
330 #define MX6_MMDC_P1_MDOTC 0x021b4008
331 #define MX6_MMDC_P1_MDCFG0 0x021b400c
332 #define MX6_MMDC_P1_MDCFG1 0x021b4010
333 #define MX6_MMDC_P1_MDCFG2 0x021b4014
334 #define MX6_MMDC_P1_MDMISC 0x021b4018
335 #define MX6_MMDC_P1_MDSCR 0x021b401c
336 #define MX6_MMDC_P1_MDREF 0x021b4020
337 #define MX6_MMDC_P1_MDRWD 0x021b402c
338 #define MX6_MMDC_P1_MDOR 0x021b4030
339 #define MX6_MMDC_P1_MDASP 0x021b4040
340 #define MX6_MMDC_P1_MAPSR 0x021b4404
341 #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
342 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
343 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
344 #define MX6_MMDC_P1_MPODTCTRL 0x021b4818
345 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
346 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
347 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
348 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
349 #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
350 #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
351 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
352 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
353 #define MX6_MMDC_P1_MPMUR0 0x021b48b8
355 #endif /*__ASM_ARCH_MX6_DDR_H__ */