2 * Copyright (C) 2013 Boundary Devices Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __ASM_ARCH_MX6_DDR_H__
7 #define __ASM_ARCH_MX6_DDR_H__
9 #ifndef CONFIG_SPL_BUILD
13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
14 #include "mx6dl-ddr.h"
17 #include "mx6sx-ddr.h"
19 #error "Please select cpu"
20 #endif /* CONFIG_MX6SX */
21 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
22 #endif /* CONFIG_MX6Q */
25 /* MMDC P0/P1 Registers */
66 * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
68 #define MX6DQ_IOM_DDR_BASE 0x020e0500
69 struct mx6dq_iomux_ddr_regs {
103 #define MX6DQ_IOM_GRP_BASE 0x020e0700
104 struct mx6dq_iomux_grp_regs {
126 #define MX6SDL_IOM_DDR_BASE 0x020e0400
127 struct mx6sdl_iomux_ddr_regs {
159 #define MX6SDL_IOM_GRP_BASE 0x020e0700
160 struct mx6sdl_iomux_grp_regs {
181 /* Device Information: Varies per DDR3 part number and speed grade */
182 struct mx6_ddr3_cfg {
183 u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
184 u8 density; /* chip density (Gb) (1,2,4,8) */
185 u8 width; /* bus width (bits) (4,8,16) */
186 u8 banks; /* number of banks */
187 u8 rowaddr; /* row address bits (11-16)*/
188 u8 coladdr; /* col address bits (9-12) */
189 u8 pagesz; /* page size (K) (1-2) */
190 u16 trcd; /* tRCD=tRP=CL (ns*100) */
191 u16 trcmin; /* tRC min (ns*100) */
192 u16 trasmin; /* tRAS min (ns*100) */
193 u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
196 /* System Information: Varies per board design, layout, and term choices */
197 struct mx6_ddr_sysinfo {
198 u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
199 u8 cs_density; /* density per chip select (Gb) */
200 u8 ncs; /* number chip selects used (1|2) */
201 char cs1_mirror;/* enable address mirror (0|1) */
202 char bi_on; /* Bank interleaving enable */
203 u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
204 u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
205 u8 ralat; /* Read Additional Latency (0-7) */
206 u8 walat; /* Write Additional Latency (0-3) */
207 u8 mif3_mode; /* Command prediction working mode */
208 u8 rst_to_cke; /* Time from SDE enable to CKE rise */
209 u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
213 * Board specific calibration:
214 * This includes write leveling calibration values as well as DQS gating
215 * and read/write delays. These values are board/layout/device specific.
216 * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
217 * (DOC-96412) to determine these values over a range of boards and
220 struct mx6_mmdc_calibration {
221 /* write leveling calibration */
226 /* read DQS gating */
239 /* configure iomux (pinctl/padctl) */
240 void mx6dq_dram_iocfg(unsigned width,
241 const struct mx6dq_iomux_ddr_regs *,
242 const struct mx6dq_iomux_grp_regs *);
243 void mx6sdl_dram_iocfg(unsigned width,
244 const struct mx6sdl_iomux_ddr_regs *,
245 const struct mx6sdl_iomux_grp_regs *);
247 /* configure mx6 mmdc registers */
248 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
249 const struct mx6_mmdc_calibration *,
250 const struct mx6_ddr3_cfg *);
252 #endif /* CONFIG_SPL_BUILD */
254 #define MX6_MMDC_P0_MDCTL 0x021b0000
255 #define MX6_MMDC_P0_MDPDC 0x021b0004
256 #define MX6_MMDC_P0_MDOTC 0x021b0008
257 #define MX6_MMDC_P0_MDCFG0 0x021b000c
258 #define MX6_MMDC_P0_MDCFG1 0x021b0010
259 #define MX6_MMDC_P0_MDCFG2 0x021b0014
260 #define MX6_MMDC_P0_MDMISC 0x021b0018
261 #define MX6_MMDC_P0_MDSCR 0x021b001c
262 #define MX6_MMDC_P0_MDREF 0x021b0020
263 #define MX6_MMDC_P0_MDRWD 0x021b002c
264 #define MX6_MMDC_P0_MDOR 0x021b0030
265 #define MX6_MMDC_P0_MDASP 0x021b0040
266 #define MX6_MMDC_P0_MAPSR 0x021b0404
267 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
268 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
269 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
270 #define MX6_MMDC_P0_MPODTCTRL 0x021b0818
271 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
272 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
273 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
274 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
275 #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
276 #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
277 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
278 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
279 #define MX6_MMDC_P0_MPMUR0 0x021b08b8
281 #define MX6_MMDC_P1_MDCTL 0x021b4000
282 #define MX6_MMDC_P1_MDPDC 0x021b4004
283 #define MX6_MMDC_P1_MDOTC 0x021b4008
284 #define MX6_MMDC_P1_MDCFG0 0x021b400c
285 #define MX6_MMDC_P1_MDCFG1 0x021b4010
286 #define MX6_MMDC_P1_MDCFG2 0x021b4014
287 #define MX6_MMDC_P1_MDMISC 0x021b4018
288 #define MX6_MMDC_P1_MDSCR 0x021b401c
289 #define MX6_MMDC_P1_MDREF 0x021b4020
290 #define MX6_MMDC_P1_MDRWD 0x021b402c
291 #define MX6_MMDC_P1_MDOR 0x021b4030
292 #define MX6_MMDC_P1_MDASP 0x021b4040
293 #define MX6_MMDC_P1_MAPSR 0x021b4404
294 #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
295 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
296 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
297 #define MX6_MMDC_P1_MPODTCTRL 0x021b4818
298 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
299 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
300 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
301 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
302 #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
303 #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
304 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
305 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
306 #define MX6_MMDC_P1_MPMUR0 0x021b48b8
308 #endif /*__ASM_ARCH_MX6_DDR_H__ */