2 * Copyright (C) 2013 Boundary Devices Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __ASM_ARCH_MX6_DDR_H__
7 #define __ASM_ARCH_MX6_DDR_H__
9 #ifndef CONFIG_SPL_BUILD
13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
14 #include "mx6dl-ddr.h"
17 #include "mx6sx-ddr.h"
20 #include "mx6ul-ddr.h"
22 #error "Please select cpu"
23 #endif /* CONFIG_MX6UL */
24 #endif /* CONFIG_MX6SX */
25 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
26 #endif /* CONFIG_MX6Q */
29 /* MMDC P0/P1 Registers */
69 #define MX6UL_IOM_DDR_BASE 0x020e0200
70 struct mx6ul_iomux_ddr_regs {
92 #define MX6UL_IOM_GRP_BASE 0x020e0400
93 struct mx6ul_iomux_grp_regs {
107 #define MX6SX_IOM_DDR_BASE 0x020e0200
108 struct mx6sx_iomux_ddr_regs {
133 #define MX6SX_IOM_GRP_BASE 0x020e0500
134 struct mx6sx_iomux_grp_regs {
151 * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
153 #define MX6DQ_IOM_DDR_BASE 0x020e0500
154 struct mx6dq_iomux_ddr_regs {
188 #define MX6DQ_IOM_GRP_BASE 0x020e0700
189 struct mx6dq_iomux_grp_regs {
211 #define MX6SDL_IOM_DDR_BASE 0x020e0400
212 struct mx6sdl_iomux_ddr_regs {
244 #define MX6SDL_IOM_GRP_BASE 0x020e0700
245 struct mx6sdl_iomux_grp_regs {
266 /* Device Information: Varies per DDR3 part number and speed grade */
267 struct mx6_ddr3_cfg {
268 u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
269 u8 density; /* chip density (Gb) (1,2,4,8) */
270 u8 width; /* bus width (bits) (4,8,16) */
271 u8 banks; /* number of banks */
272 u8 rowaddr; /* row address bits (11-16)*/
273 u8 coladdr; /* col address bits (9-12) */
274 u8 pagesz; /* page size (K) (1-2) */
275 u16 trcd; /* tRCD=tRP=CL (ns*100) */
276 u16 trcmin; /* tRC min (ns*100) */
277 u16 trasmin; /* tRAS min (ns*100) */
278 u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
281 /* System Information: Varies per board design, layout, and term choices */
282 struct mx6_ddr_sysinfo {
283 u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
284 u8 cs_density; /* density per chip select (Gb) */
285 u8 ncs; /* number chip selects used (1|2) */
286 char cs1_mirror;/* enable address mirror (0|1) */
287 char bi_on; /* Bank interleaving enable */
288 u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
289 u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
290 u8 ralat; /* Read Additional Latency (0-7) */
291 u8 walat; /* Write Additional Latency (0-3) */
292 u8 mif3_mode; /* Command prediction working mode */
293 u8 rst_to_cke; /* Time from SDE enable to CKE rise */
294 u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
295 u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
299 * Board specific calibration:
300 * This includes write leveling calibration values as well as DQS gating
301 * and read/write delays. These values are board/layout/device specific.
302 * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
303 * (DOC-96412) to determine these values over a range of boards and
306 struct mx6_mmdc_calibration {
307 /* write leveling calibration */
312 /* read DQS gating */
325 /* configure iomux (pinctl/padctl) */
326 void mx6dq_dram_iocfg(unsigned width,
327 const struct mx6dq_iomux_ddr_regs *,
328 const struct mx6dq_iomux_grp_regs *);
329 void mx6sdl_dram_iocfg(unsigned width,
330 const struct mx6sdl_iomux_ddr_regs *,
331 const struct mx6sdl_iomux_grp_regs *);
332 void mx6sx_dram_iocfg(unsigned width,
333 const struct mx6sx_iomux_ddr_regs *,
334 const struct mx6sx_iomux_grp_regs *);
335 void mx6ul_dram_iocfg(unsigned width,
336 const struct mx6ul_iomux_ddr_regs *,
337 const struct mx6ul_iomux_grp_regs *);
339 /* configure mx6 mmdc registers */
340 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
341 const struct mx6_mmdc_calibration *,
342 const struct mx6_ddr3_cfg *);
344 #endif /* CONFIG_SPL_BUILD */
346 #define MX6_MMDC_P0_MDCTL 0x021b0000
347 #define MX6_MMDC_P0_MDPDC 0x021b0004
348 #define MX6_MMDC_P0_MDOTC 0x021b0008
349 #define MX6_MMDC_P0_MDCFG0 0x021b000c
350 #define MX6_MMDC_P0_MDCFG1 0x021b0010
351 #define MX6_MMDC_P0_MDCFG2 0x021b0014
352 #define MX6_MMDC_P0_MDMISC 0x021b0018
353 #define MX6_MMDC_P0_MDSCR 0x021b001c
354 #define MX6_MMDC_P0_MDREF 0x021b0020
355 #define MX6_MMDC_P0_MDRWD 0x021b002c
356 #define MX6_MMDC_P0_MDOR 0x021b0030
357 #define MX6_MMDC_P0_MDASP 0x021b0040
358 #define MX6_MMDC_P0_MAPSR 0x021b0404
359 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
360 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
361 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
362 #define MX6_MMDC_P0_MPODTCTRL 0x021b0818
363 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
364 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
365 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
366 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
367 #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
368 #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
369 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
370 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
371 #define MX6_MMDC_P0_MPMUR0 0x021b08b8
373 #define MX6_MMDC_P1_MDCTL 0x021b4000
374 #define MX6_MMDC_P1_MDPDC 0x021b4004
375 #define MX6_MMDC_P1_MDOTC 0x021b4008
376 #define MX6_MMDC_P1_MDCFG0 0x021b400c
377 #define MX6_MMDC_P1_MDCFG1 0x021b4010
378 #define MX6_MMDC_P1_MDCFG2 0x021b4014
379 #define MX6_MMDC_P1_MDMISC 0x021b4018
380 #define MX6_MMDC_P1_MDSCR 0x021b401c
381 #define MX6_MMDC_P1_MDREF 0x021b4020
382 #define MX6_MMDC_P1_MDRWD 0x021b402c
383 #define MX6_MMDC_P1_MDOR 0x021b4030
384 #define MX6_MMDC_P1_MDASP 0x021b4040
385 #define MX6_MMDC_P1_MAPSR 0x021b4404
386 #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
387 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
388 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
389 #define MX6_MMDC_P1_MPODTCTRL 0x021b4818
390 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
391 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
392 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
393 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
394 #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
395 #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
396 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
397 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
398 #define MX6_MMDC_P1_MPMUR0 0x021b48b8
400 #endif /*__ASM_ARCH_MX6_DDR_H__ */