2 * Copyright (C) 2013 Boundary Devices Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __ASM_ARCH_MX6_DDR_H__
7 #define __ASM_ARCH_MX6_DDR_H__
9 #ifndef CONFIG_SPL_BUILD
13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
14 #include "mx6dl-ddr.h"
16 #error "Please select cpu"
17 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
18 #endif /* CONFIG_MX6Q */
21 /* MMDC P0/P1 Registers */
62 * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
64 #define MX6DQ_IOM_DDR_BASE 0x020e0500
65 struct mx6dq_iomux_ddr_regs {
99 #define MX6DQ_IOM_GRP_BASE 0x020e0700
100 struct mx6dq_iomux_grp_regs {
122 #define MX6SDL_IOM_DDR_BASE 0x020e0400
123 struct mx6sdl_iomux_ddr_regs {
155 #define MX6SDL_IOM_GRP_BASE 0x020e0700
156 struct mx6sdl_iomux_grp_regs {
176 #endif /* CONFIG_SPL_BUILD */
178 #define MX6_MMDC_P0_MDCTL 0x021b0000
179 #define MX6_MMDC_P0_MDPDC 0x021b0004
180 #define MX6_MMDC_P0_MDOTC 0x021b0008
181 #define MX6_MMDC_P0_MDCFG0 0x021b000c
182 #define MX6_MMDC_P0_MDCFG1 0x021b0010
183 #define MX6_MMDC_P0_MDCFG2 0x021b0014
184 #define MX6_MMDC_P0_MDMISC 0x021b0018
185 #define MX6_MMDC_P0_MDSCR 0x021b001c
186 #define MX6_MMDC_P0_MDREF 0x021b0020
187 #define MX6_MMDC_P0_MDRWD 0x021b002c
188 #define MX6_MMDC_P0_MDOR 0x021b0030
189 #define MX6_MMDC_P0_MDASP 0x021b0040
190 #define MX6_MMDC_P0_MAPSR 0x021b0404
191 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
192 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
193 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
194 #define MX6_MMDC_P0_MPODTCTRL 0x021b0818
195 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
196 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
197 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
198 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
199 #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
200 #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
201 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
202 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
203 #define MX6_MMDC_P0_MPMUR0 0x021b08b8
205 #define MX6_MMDC_P1_MDCTL 0x021b4000
206 #define MX6_MMDC_P1_MDPDC 0x021b4004
207 #define MX6_MMDC_P1_MDOTC 0x021b4008
208 #define MX6_MMDC_P1_MDCFG0 0x021b400c
209 #define MX6_MMDC_P1_MDCFG1 0x021b4010
210 #define MX6_MMDC_P1_MDCFG2 0x021b4014
211 #define MX6_MMDC_P1_MDMISC 0x021b4018
212 #define MX6_MMDC_P1_MDSCR 0x021b401c
213 #define MX6_MMDC_P1_MDREF 0x021b4020
214 #define MX6_MMDC_P1_MDRWD 0x021b402c
215 #define MX6_MMDC_P1_MDOR 0x021b4030
216 #define MX6_MMDC_P1_MDASP 0x021b4040
217 #define MX6_MMDC_P1_MAPSR 0x021b4404
218 #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
219 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
220 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
221 #define MX6_MMDC_P1_MPODTCTRL 0x021b4818
222 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
223 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
224 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
225 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
226 #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
227 #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
228 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
229 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
230 #define MX6_MMDC_P1_MPMUR0 0x021b48b8
232 #endif /*__ASM_ARCH_MX6_DDR_H__ */