1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013 Boundary Devices Inc.
5 #ifndef __ASM_ARCH_MX6_DDR_H__
6 #define __ASM_ARCH_MX6_DDR_H__
8 #ifndef CONFIG_SPL_BUILD
12 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
13 #include "mx6dl-ddr.h"
16 #include "mx6sx-ddr.h"
18 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
19 #include "mx6ul-ddr.h"
22 #include "mx6sl-ddr.h"
24 #error "Please select cpu"
25 #endif /* CONFIG_MX6SL */
26 #endif /* CONFIG_MX6UL */
27 #endif /* CONFIG_MX6SX */
28 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
29 #endif /* CONFIG_MX6Q */
37 /* MMDC P0/P1 Registers */
124 #define MX6SL_IOM_DDR_BASE 0x020e0300
125 struct mx6sl_iomux_ddr_regs {
150 #define MX6SL_IOM_GRP_BASE 0x020e0500
151 struct mx6sl_iomux_grp_regs {
167 #define MX6UL_IOM_DDR_BASE 0x020e0200
168 struct mx6ul_iomux_ddr_regs {
190 #define MX6UL_IOM_GRP_BASE 0x020e0400
191 struct mx6ul_iomux_grp_regs {
205 #define MX6SX_IOM_DDR_BASE 0x020e0200
206 struct mx6sx_iomux_ddr_regs {
231 #define MX6SX_IOM_GRP_BASE 0x020e0500
232 struct mx6sx_iomux_grp_regs {
249 * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
251 #define MX6DQ_IOM_DDR_BASE 0x020e0500
252 struct mx6dq_iomux_ddr_regs {
286 #define MX6DQ_IOM_GRP_BASE 0x020e0700
287 struct mx6dq_iomux_grp_regs {
309 #define MX6SDL_IOM_DDR_BASE 0x020e0400
310 struct mx6sdl_iomux_ddr_regs {
342 #define MX6SDL_IOM_GRP_BASE 0x020e0700
343 struct mx6sdl_iomux_grp_regs {
364 /* Device Information: Varies per DDR3 part number and speed grade */
365 struct mx6_ddr3_cfg {
366 u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
367 u8 density; /* chip density (Gb) (1,2,4,8) */
368 u8 width; /* bus width (bits) (4,8,16) */
369 u8 banks; /* number of banks */
370 u8 rowaddr; /* row address bits (11-16)*/
371 u8 coladdr; /* col address bits (9-12) */
372 u8 pagesz; /* page size (K) (1-2) */
373 u16 trcd; /* tRCD=tRP=CL (ns*100) */
374 u16 trcmin; /* tRC min (ns*100) */
375 u16 trasmin; /* tRAS min (ns*100) */
376 u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
379 /* Device Information: Varies per LPDDR2 part number and speed grade */
380 struct mx6_lpddr2_cfg {
381 u16 mem_speed; /* ie 800 for LPDDR2-800 */
382 u8 density; /* chip density (Gb) (1,2,4,8) */
383 u8 width; /* bus width (bits) (4,8,16) */
384 u8 banks; /* number of banks */
385 u8 rowaddr; /* row address bits (11-16)*/
386 u8 coladdr; /* col address bits (9-12) */
390 u16 trcmin; /* tRC min (ns*100) */
391 u16 trasmin; /* tRAS min (ns*100) */
394 /* System Information: Varies per board design, layout, and term choices */
395 struct mx6_ddr_sysinfo {
396 u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
397 u8 cs_density; /* density per chip select (Gb) */
398 u8 ncs; /* number chip selects used (1|2) */
399 char cs1_mirror;/* enable address mirror (0|1) */
400 char bi_on; /* Bank interleaving enable */
401 u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
402 u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
403 u8 ralat; /* Read Additional Latency (0-7) */
404 u8 walat; /* Write Additional Latency (0-3) */
405 u8 mif3_mode; /* Command prediction working mode */
406 u8 rst_to_cke; /* Time from SDE enable to CKE rise */
407 u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
408 u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
409 u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */
410 u8 refsel; /* REF_SEL field of register MDREF */
411 u8 refr; /* REFR field of register MDREF */
415 * Board specific calibration:
416 * This includes write leveling calibration values as well as DQS gating
417 * and read/write delays. These values are board/layout/device specific.
418 * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
419 * (DOC-96412) to determine these values over a range of boards and
422 struct mx6_mmdc_calibration {
423 /* write leveling calibration */
428 /* read DQS gating */
439 /* lpddr2 zq hw calibration */
443 /* configure iomux (pinctl/padctl) */
444 void mx6dq_dram_iocfg(unsigned width,
445 const struct mx6dq_iomux_ddr_regs *,
446 const struct mx6dq_iomux_grp_regs *);
447 void mx6sdl_dram_iocfg(unsigned width,
448 const struct mx6sdl_iomux_ddr_regs *,
449 const struct mx6sdl_iomux_grp_regs *);
450 void mx6sx_dram_iocfg(unsigned width,
451 const struct mx6sx_iomux_ddr_regs *,
452 const struct mx6sx_iomux_grp_regs *);
453 void mx6ul_dram_iocfg(unsigned width,
454 const struct mx6ul_iomux_ddr_regs *,
455 const struct mx6ul_iomux_grp_regs *);
456 void mx6sl_dram_iocfg(unsigned width,
457 const struct mx6sl_iomux_ddr_regs *,
458 const struct mx6sl_iomux_grp_regs *);
460 #if defined(CONFIG_MX6_DDRCAL)
461 int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
462 int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
463 void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
464 struct mx6_mmdc_calibration *calib);
467 /* configure mx6 mmdc registers */
468 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
469 const struct mx6_mmdc_calibration *,
472 #endif /* CONFIG_SPL_BUILD */
474 #define MX6_MMDC_P0_MDCTL 0x021b0000
475 #define MX6_MMDC_P0_MDPDC 0x021b0004
476 #define MX6_MMDC_P0_MDOTC 0x021b0008
477 #define MX6_MMDC_P0_MDCFG0 0x021b000c
478 #define MX6_MMDC_P0_MDCFG1 0x021b0010
479 #define MX6_MMDC_P0_MDCFG2 0x021b0014
480 #define MX6_MMDC_P0_MDMISC 0x021b0018
481 #define MX6_MMDC_P0_MDSCR 0x021b001c
482 #define MX6_MMDC_P0_MDREF 0x021b0020
483 #define MX6_MMDC_P0_MDRWD 0x021b002c
484 #define MX6_MMDC_P0_MDOR 0x021b0030
485 #define MX6_MMDC_P0_MDASP 0x021b0040
486 #define MX6_MMDC_P0_MAPSR 0x021b0404
487 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
488 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
489 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
490 #define MX6_MMDC_P0_MPODTCTRL 0x021b0818
491 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
492 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
493 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
494 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
495 #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
496 #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
497 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
498 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
499 #define MX6_MMDC_P0_MPZQLP2CTL 0x021b085C
500 #define MX6_MMDC_P0_MPMUR0 0x021b08b8
502 #define MX6_MMDC_P1_MDCTL 0x021b4000
503 #define MX6_MMDC_P1_MDPDC 0x021b4004
504 #define MX6_MMDC_P1_MDOTC 0x021b4008
505 #define MX6_MMDC_P1_MDCFG0 0x021b400c
506 #define MX6_MMDC_P1_MDCFG1 0x021b4010
507 #define MX6_MMDC_P1_MDCFG2 0x021b4014
508 #define MX6_MMDC_P1_MDMISC 0x021b4018
509 #define MX6_MMDC_P1_MDSCR 0x021b401c
510 #define MX6_MMDC_P1_MDREF 0x021b4020
511 #define MX6_MMDC_P1_MDRWD 0x021b402c
512 #define MX6_MMDC_P1_MDOR 0x021b4030
513 #define MX6_MMDC_P1_MDASP 0x021b4040
514 #define MX6_MMDC_P1_MAPSR 0x021b4404
515 #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
516 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
517 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
518 #define MX6_MMDC_P1_MPODTCTRL 0x021b4818
519 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
520 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
521 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
522 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
523 #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
524 #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
525 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
526 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
527 #define MX6_MMDC_P1_MPZQLP2CTL 0x021b485C
528 #define MX6_MMDC_P1_MPMUR0 0x021b48b8
530 #endif /*__ASM_ARCH_MX6_DDR_H__ */