3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/imx-common/regs-common.h>
12 #include "../arch-imx/cpu.h"
14 #define soc_rev() (get_cpu_rev() & 0xFF)
15 #define is_soc_rev(rev) (soc_rev() == rev)
17 u32 get_nr_cpus(void);
18 u32 get_cpu_rev(void);
19 u32 get_cpu_speed_grade_hz(void);
20 u32 get_cpu_temp_grade(int *minc, int *maxc);
22 /* returns MXC_CPU_ value */
23 #define cpu_type(rev) (((rev) >> 12) & 0xff)
25 /* both macros return/take MXC_CPU_ constants */
26 #define get_cpu_type() (cpu_type(get_cpu_rev()))
27 #define is_cpu_type(cpu) (get_cpu_type() == cpu)
29 const char *get_imx_type(u32 imxtype);
30 unsigned imx_ddr_size(void);
31 void set_chipselect_size(int const);
33 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
36 * Initializes on-chip ethernet controllers.
37 * to override, implement board_eth_init()
40 int fecmxc_initialize(bd_t *bis);
41 u32 get_ahb_clk(void);
42 u32 get_periph_clk(void);
44 int mxs_reset_block(struct mxs_register_32 *reg);
45 int mxs_wait_mask_set(struct mxs_register_32 *reg,
47 unsigned int timeout);
48 int mxs_wait_mask_clr(struct mxs_register_32 *reg,
50 unsigned int timeout);