git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-mx7/clock.h

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * Author:
   5  *      Peng Fan <Peng.Fan@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _ASM_ARCH_CLOCK_H
  11 #define _ASM_ARCH_CLOCK_H
  12
  13 #include <common.h>
  14 #include <asm/arch/crm_regs.h>
  15
  16 #ifdef CONFIG_SYS_MX7_HCLK
  17 #define MXC_HCLK        CONFIG_SYS_MX7_HCLK
  18 #else
  19 #define MXC_HCLK        24000000
  20 #endif
  21
  22 #ifdef CONFIG_SYS_MX7_CLK32
  23 #define MXC_CLK32       CONFIG_SYS_MX7_CLK32
  24 #else
  25 #define MXC_CLK32       32768
  26 #endif
  27
  28 /* Mainly for compatible to imx common code. */
  29 enum mxc_clock {
  30         MXC_ARM_CLK = 0,
  31         MXC_AHB_CLK,
  32         MXC_IPG_CLK,
  33         MXC_UART_CLK,
  34         MXC_CSPI_CLK,
  35         MXC_AXI_CLK,
  36         MXC_DDR_CLK,
  37         MXC_ESDHC_CLK,
  38         MXC_ESDHC2_CLK,
  39         MXC_ESDHC3_CLK,
  40         MXC_I2C_CLK,
  41 };
  42
  43 /* PLL supported by i.mx7d */
  44 enum pll_clocks {
  45         PLL_CORE,       /* Core PLL */
  46         PLL_SYS,        /* System PLL*/
  47         PLL_ENET,       /* Enet PLL */
  48         PLL_AUDIO,      /* Audio PLL */
  49         PLL_VIDEO,      /* Video PLL*/
  50         PLL_DDR,        /* Dram PLL */
  51         PLL_USB,        /* USB PLL, fixed at 480MHZ */
  52 };
  53
  54 /* clk src for clock root gen */
  55 enum clk_root_src {
  56         OSC_24M_CLK,
  57
  58         PLL_ARM_MAIN_800M_CLK,
  59
  60         PLL_SYS_MAIN_480M_CLK,
  61         PLL_SYS_MAIN_240M_CLK,
  62         PLL_SYS_MAIN_120M_CLK,
  63         PLL_SYS_PFD0_392M_CLK,
  64         PLL_SYS_PFD0_196M_CLK,
  65         PLL_SYS_PFD1_332M_CLK,
  66         PLL_SYS_PFD1_166M_CLK,
  67         PLL_SYS_PFD2_270M_CLK,
  68         PLL_SYS_PFD2_135M_CLK,
  69         PLL_SYS_PFD3_CLK,
  70         PLL_SYS_PFD4_CLK,
  71         PLL_SYS_PFD5_CLK,
  72         PLL_SYS_PFD6_CLK,
  73         PLL_SYS_PFD7_CLK,
  74
  75         PLL_ENET_MAIN_500M_CLK,
  76         PLL_ENET_MAIN_250M_CLK,
  77         PLL_ENET_MAIN_125M_CLK,
  78         PLL_ENET_MAIN_100M_CLK,
  79         PLL_ENET_MAIN_50M_CLK,
  80         PLL_ENET_MAIN_40M_CLK,
  81         PLL_ENET_MAIN_25M_CLK,
  82
  83         PLL_DRAM_MAIN_1066M_CLK,
  84         PLL_DRAM_MAIN_533M_CLK,
  85
  86         PLL_AUDIO_MAIN_CLK,
  87         PLL_VIDEO_MAIN_CLK,
  88
  89         PLL_USB_MAIN_480M_CLK,          /* fixed at 480MHZ */
  90
  91         EXT_CLK_1,
  92         EXT_CLK_2,
  93         EXT_CLK_3,
  94         EXT_CLK_4,
  95
  96         REF_1M_CLK,
  97         OSC_32K_CLK,
  98 };
  99
 100 /*
 101  * Clock root index
 102  */
 103 enum clk_root_index {
 104         ARM_A7_CLK_ROOT = 0,
 105         ARM_M4_CLK_ROOT = 1,
 106         ARM_M0_CLK_ROOT = 2,
 107         MAIN_AXI_CLK_ROOT = 16,
 108         DISP_AXI_CLK_ROOT = 17,
 109         ENET_AXI_CLK_ROOT = 18,
 110         NAND_USDHC_BUS_CLK_ROOT = 19,
 111         AHB_CLK_ROOT = 32,
 112         DRAM_PHYM_CLK_ROOT = 48,
 113         DRAM_CLK_ROOT = 49,
 114         DRAM_PHYM_ALT_CLK_ROOT = 64,
 115         DRAM_ALT_CLK_ROOT = 65,
 116         USB_HSIC_CLK_ROOT = 66,
 117         PCIE_CTRL_CLK_ROOT = 67,
 118         PCIE_PHY_CLK_ROOT = 68,
 119         EPDC_PIXEL_CLK_ROOT = 69,
 120         LCDIF_PIXEL_CLK_ROOT = 70,
 121         MIPI_DSI_EXTSER_CLK_ROOT = 71,
 122         MIPI_CSI_WARP_CLK_ROOT = 72,
 123         MIPI_DPHY_REF_CLK_ROOT = 73,
 124         SAI1_CLK_ROOT = 74,
 125         SAI2_CLK_ROOT = 75,
 126         SAI3_CLK_ROOT = 76,
 127         SPDIF_CLK_ROOT = 77,
 128         ENET1_REF_CLK_ROOT = 78,
 129         ENET1_TIME_CLK_ROOT = 79,
 130         ENET2_REF_CLK_ROOT = 80,
 131         ENET2_TIME_CLK_ROOT = 81,
 132         ENET_PHY_REF_CLK_ROOT = 82,
 133         EIM_CLK_ROOT = 83,
 134         NAND_CLK_ROOT = 84,
 135         QSPI_CLK_ROOT = 85,
 136         USDHC1_CLK_ROOT = 86,
 137         USDHC2_CLK_ROOT = 87,
 138         USDHC3_CLK_ROOT = 88,
 139         CAN1_CLK_ROOT = 89,
 140         CAN2_CLK_ROOT = 90,
 141         I2C1_CLK_ROOT = 91,
 142         I2C2_CLK_ROOT = 92,
 143         I2C3_CLK_ROOT = 93,
 144         I2C4_CLK_ROOT = 94,
 145         UART1_CLK_ROOT = 95,
 146         UART2_CLK_ROOT = 96,
 147         UART3_CLK_ROOT = 97,
 148         UART4_CLK_ROOT = 98,
 149         UART5_CLK_ROOT = 99,
 150         UART6_CLK_ROOT = 100,
 151         UART7_CLK_ROOT = 101,
 152         ECSPI1_CLK_ROOT = 102,
 153         ECSPI2_CLK_ROOT = 103,
 154         ECSPI3_CLK_ROOT = 104,
 155         ECSPI4_CLK_ROOT = 105,
 156         PWM1_CLK_ROOT = 106,
 157         PWM2_CLK_ROOT = 107,
 158         PWM3_CLK_ROOT = 108,
 159         PWM4_CLK_ROOT = 109,
 160         FLEXTIMER1_CLK_ROOT = 110,
 161         FLEXTIMER2_CLK_ROOT = 111,
 162         SIM1_CLK_ROOT = 112,
 163         SIM2_CLK_ROOT = 113,
 164         GPT1_CLK_ROOT = 114,
 165         GPT2_CLK_ROOT = 115,
 166         GPT3_CLK_ROOT = 116,
 167         GPT4_CLK_ROOT = 117,
 168         TRACE_CLK_ROOT = 118,
 169         WDOG_CLK_ROOT = 119,
 170         CSI_MCLK_CLK_ROOT = 120,
 171         AUDIO_MCLK_CLK_ROOT = 121,
 172         WRCLK_CLK_ROOT = 122,
 173         IPP_DO_CLKO1 = 123,
 174         IPP_DO_CLKO2 = 124,
 175
 176         CLK_ROOT_MAX,
 177 };
 178
 179 struct clk_root_setting {
 180         enum clk_root_index root;
 181         u32 setting;
 182 };
 183
 184 /*
 185  * CCGR mapping
 186  */
 187 enum clk_ccgr_index {
 188         CCGR_CPU = 0,
 189         CCGR_M4 = 1,
 190         CCGR_SIM_MAIN = 4,
 191         CCGR_SIM_DISPLAY = 5,
 192         CCGR_SIM_ENET = 6,
 193         CCGR_SIM_M = 7,
 194         CCGR_SIM_S = 8,
 195         CCGR_SIM_WAKEUP = 9,
 196         CCGR_IPMUX1 = 10,
 197         CCGR_IPMUX2 = 11,
 198         CCGR_IPMUX3 = 12,
 199         CCGR_ROM = 16,
 200         CCGR_OCRAM = 17,
 201         CCGR_OCRAM_S = 18,
 202         CCGR_DRAM = 19,
 203         CCGR_RAWNAND = 20,
 204         CCGR_QSPI = 21,
 205         CCGR_WEIM = 22,
 206         CCGR_ADC = 32,
 207         CCGR_ANATOP = 33,
 208         CCGR_SCTR = 34,
 209         CCGR_OCOTP = 35,
 210         CCGR_CAAM = 36,
 211         CCGR_SNVS = 37,
 212         CCGR_RDC = 38,
 213         CCGR_MU = 39,
 214         CCGR_HS = 40,
 215         CCGR_DVFS = 41,
 216         CCGR_QOS = 42,
 217         CCGR_QOS_DISPMIX = 43,
 218         CCGR_QOS_MEGAMIX = 44,
 219         CCGR_CSU = 45,
 220         CCGR_DBGMON = 46,
 221         CCGR_DEBUG = 47,
 222         CCGR_TRACE = 48,
 223         CCGR_SEC_DEBUG = 49,
 224         CCGR_SEMA1 = 64,
 225         CCGR_SEMA2 = 65,
 226         CCGR_PERFMON1 = 68,
 227         CCGR_PERFMON2 = 69,
 228         CCGR_SDMA = 72,
 229         CCGR_CSI = 73,
 230         CCGR_EPDC = 74,
 231         CCGR_LCDIF = 75,
 232         CCGR_PXP = 76,
 233         CCGR_PCIE = 96,
 234         CCGR_MIPI_CSI = 100,
 235         CCGR_MIPI_DSI = 101,
 236         CCGR_MIPI_MEM_PHY = 102,
 237         CCGR_USB_CTRL = 104,
 238         CCGR_USB_HSIC = 105,
 239         CCGR_USB_PHY1 = 106,
 240         CCGR_USB_PHY2 = 107,
 241         CCGR_USDHC1 = 108,
 242         CCGR_USDHC2 = 109,
 243         CCGR_USDHC3 = 110,
 244         CCGR_ENET1 = 112,
 245         CCGR_ENET2 = 113,
 246         CCGR_CAN1 = 116,
 247         CCGR_CAN2 = 117,
 248         CCGR_ECSPI1 = 120,
 249         CCGR_ECSPI2 = 121,
 250         CCGR_ECSPI3 = 122,
 251         CCGR_ECSPI4 = 123,
 252         CCGR_GPT1 = 124,
 253         CCGR_GPT2 = 125,
 254         CCGR_GPT3 = 126,
 255         CCGR_GPT4 = 127,
 256         CCGR_FTM1 = 128,
 257         CCGR_FTM2 = 129,
 258         CCGR_PWM1 = 132,
 259         CCGR_PWM2 = 133,
 260         CCGR_PWM3 = 134,
 261         CCGR_PWM4 = 135,
 262         CCGR_I2C1 = 136,
 263         CCGR_I2C2 = 137,
 264         CCGR_I2C3 = 138,
 265         CCGR_I2C4 = 139,
 266         CCGR_SAI1 = 140,
 267         CCGR_SAI2 = 141,
 268         CCGR_SAI3 = 142,
 269         CCGR_SIM1 = 144,
 270         CCGR_SIM2 = 145,
 271         CCGR_UART1 = 148,
 272         CCGR_UART2 = 149,
 273         CCGR_UART3 = 150,
 274         CCGR_UART4 = 151,
 275         CCGR_UART5 = 152,
 276         CCGR_UART6 = 153,
 277         CCGR_UART7 = 154,
 278         CCGR_WDOG1 = 156,
 279         CCGR_WDOG2 = 157,
 280         CCGR_WDOG3 = 158,
 281         CCGR_WDOG4 = 159,
 282         CCGR_GPIO1 = 160,
 283         CCGR_GPIO2 = 161,
 284         CCGR_GPIO3 = 162,
 285         CCGR_GPIO4 = 163,
 286         CCGR_GPIO5 = 164,
 287         CCGR_GPIO6 = 165,
 288         CCGR_GPIO7 = 166,
 289         CCGR_IOMUX = 168,
 290         CCGR_IOMUX_LPSR = 169,
 291         CCGR_KPP = 170,
 292
 293         CCGR_SKIP,
 294         CCGR_MAX,
 295 };
 296
 297 /* Clock root channel */
 298 enum clk_root_type {
 299         CCM_CORE_CHANNEL,
 300         CCM_BUS_CHANNEL,
 301         CCM_AHB_CHANNEL,
 302         CCM_DRAM_PHYM_CHANNEL,
 303         CCM_DRAM_CHANNEL,
 304         CCM_IP_CHANNEL,
 305 };
 306
 307 #include <asm/arch/clock_slice.h>
 308
 309 /*
 310  * entry: the clock root index
 311  * type: ccm channel
 312  * src_mux: each entry corresponding to the clock src, detailed info in CCM RM
 313  */
 314 struct clk_root_map {
 315         enum clk_root_index entry;
 316         enum clk_root_type type;
 317         uint8_t src_mux[8];
 318 };
 319
 320 enum enet_freq {
 321         ENET_25MHZ,
 322         ENET_50MHZ,
 323         ENET_125MHZ,
 324 };
 325
 326 u32 get_root_clk(enum clk_root_index clock_id);
 327 u32 mxc_get_clock(enum mxc_clock clk);
 328 u32 imx_get_uartclk(void);
 329 u32 imx_get_fecclk(void);
 330 void clock_init(void);
 331 #ifdef CONFIG_SYS_I2C_MXC
 332 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 333 #endif
 334 #ifdef CONFIG_FEC_MXC
 335 int set_clk_enet(enum enet_freq type);
 336 #endif
 337 int set_clk_qspi(void);
 338 int set_clk_nand(void);
 339 #ifdef CONFIG_MXC_OCOTP
 340 void enable_ocotp_clk(unsigned char enable);
 341 #endif
 342 void enable_usboh3_clk(unsigned char enable);
 343 #ifdef CONFIG_SECURE_BOOT
 344 void hab_caam_clock_enable(unsigned char enable);
 345 #endif
 346 void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
 347 void enable_thermal_clk(void);
 348 #endif