2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
5 * Peng Fan <Peng.Fan@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef _ASM_ARCH_CLOCK_H
11 #define _ASM_ARCH_CLOCK_H
14 #include <asm/arch/crm_regs.h>
16 #ifdef CONFIG_SYS_MX7_HCLK
17 #define MXC_HCLK CONFIG_SYS_MX7_HCLK
19 #define MXC_HCLK 24000000
22 #ifdef CONFIG_SYS_MX7_CLK32
23 #define MXC_CLK32 CONFIG_SYS_MX7_CLK32
25 #define MXC_CLK32 32768
28 /* Mainly for compatible to imx common code. */
43 /* PLL supported by i.mx7d */
45 PLL_CORE, /* Core PLL */
46 PLL_SYS, /* System PLL*/
47 PLL_ENET, /* Enet PLL */
48 PLL_AUDIO, /* Audio PLL */
49 PLL_VIDEO, /* Video PLL*/
50 PLL_DDR, /* Dram PLL */
51 PLL_USB, /* USB PLL, fixed at 480MHZ */
54 /* clk src for clock root gen */
58 PLL_ARM_MAIN_800M_CLK,
60 PLL_SYS_MAIN_480M_CLK,
61 PLL_SYS_MAIN_240M_CLK,
62 PLL_SYS_MAIN_120M_CLK,
63 PLL_SYS_PFD0_392M_CLK,
64 PLL_SYS_PFD0_196M_CLK,
65 PLL_SYS_PFD1_332M_CLK,
66 PLL_SYS_PFD1_166M_CLK,
67 PLL_SYS_PFD2_270M_CLK,
68 PLL_SYS_PFD2_135M_CLK,
75 PLL_ENET_MAIN_500M_CLK,
76 PLL_ENET_MAIN_250M_CLK,
77 PLL_ENET_MAIN_125M_CLK,
78 PLL_ENET_MAIN_100M_CLK,
79 PLL_ENET_MAIN_50M_CLK,
80 PLL_ENET_MAIN_40M_CLK,
81 PLL_ENET_MAIN_25M_CLK,
83 PLL_DRAM_MAIN_1066M_CLK,
84 PLL_DRAM_MAIN_533M_CLK,
89 PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */
103 enum clk_root_index {
107 MAIN_AXI_CLK_ROOT = 16,
108 DISP_AXI_CLK_ROOT = 17,
109 ENET_AXI_CLK_ROOT = 18,
110 NAND_USDHC_BUS_CLK_ROOT = 19,
112 DRAM_PHYM_CLK_ROOT = 48,
114 DRAM_PHYM_ALT_CLK_ROOT = 64,
115 DRAM_ALT_CLK_ROOT = 65,
116 USB_HSIC_CLK_ROOT = 66,
117 PCIE_CTRL_CLK_ROOT = 67,
118 PCIE_PHY_CLK_ROOT = 68,
119 EPDC_PIXEL_CLK_ROOT = 69,
120 LCDIF_PIXEL_CLK_ROOT = 70,
121 MIPI_DSI_EXTSER_CLK_ROOT = 71,
122 MIPI_CSI_WARP_CLK_ROOT = 72,
123 MIPI_DPHY_REF_CLK_ROOT = 73,
128 ENET1_REF_CLK_ROOT = 78,
129 ENET1_TIME_CLK_ROOT = 79,
130 ENET2_REF_CLK_ROOT = 80,
131 ENET2_TIME_CLK_ROOT = 81,
132 ENET_PHY_REF_CLK_ROOT = 82,
136 USDHC1_CLK_ROOT = 86,
137 USDHC2_CLK_ROOT = 87,
138 USDHC3_CLK_ROOT = 88,
150 UART6_CLK_ROOT = 100,
151 UART7_CLK_ROOT = 101,
152 ECSPI1_CLK_ROOT = 102,
153 ECSPI2_CLK_ROOT = 103,
154 ECSPI3_CLK_ROOT = 104,
155 ECSPI4_CLK_ROOT = 105,
160 FLEXTIMER1_CLK_ROOT = 110,
161 FLEXTIMER2_CLK_ROOT = 111,
168 TRACE_CLK_ROOT = 118,
170 CSI_MCLK_CLK_ROOT = 120,
171 AUDIO_MCLK_CLK_ROOT = 121,
172 WRCLK_CLK_ROOT = 122,
179 struct clk_root_setting {
180 enum clk_root_index root;
187 enum clk_ccgr_index {
191 CCGR_SIM_DISPLAY = 5,
217 CCGR_QOS_DISPMIX = 43,
218 CCGR_QOS_MEGAMIX = 44,
236 CCGR_MIPI_MEM_PHY = 102,
290 CCGR_IOMUX_LPSR = 169,
297 /* Clock root channel */
302 CCM_DRAM_PHYM_CHANNEL,
307 #include <asm/arch/clock_slice.h>
310 * entry: the clock root index
312 * src_mux: each entry corresponding to the clock src, detailed info in CCM RM
314 struct clk_root_map {
315 enum clk_root_index entry;
316 enum clk_root_type type;
326 u32 get_root_clk(enum clk_root_index clock_id);
327 u32 mxc_get_clock(enum mxc_clock clk);
328 u32 imx_get_uartclk(void);
329 u32 imx_get_fecclk(void);
330 void clock_init(void);
331 #ifdef CONFIG_SYS_I2C_MXC
332 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
334 #ifdef CONFIG_FEC_MXC
335 int set_clk_enet(enum enet_freq type);
337 int set_clk_qspi(void);
338 int set_clk_nand(void);
339 #ifdef CONFIG_MXC_OCOTP
340 void enable_ocotp_clk(unsigned char enable);
342 void enable_usboh3_clk(unsigned char enable);
343 #ifdef CONFIG_SECURE_BOOT
344 void hab_caam_clock_enable(unsigned char enable);
346 void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
347 void enable_thermal_clk(void);