1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
6 * Peng Fan <Peng.Fan@freescale.com>
9 #ifndef _ASM_ARCH_CLOCK_H
10 #define _ASM_ARCH_CLOCK_H
13 #include <asm/arch/crm_regs.h>
15 #ifdef CONFIG_SYS_MX7_HCLK
16 #define MXC_HCLK CONFIG_SYS_MX7_HCLK
18 #define MXC_HCLK 24000000
21 #ifdef CONFIG_SYS_MX7_CLK32
22 #define MXC_CLK32 CONFIG_SYS_MX7_CLK32
24 #define MXC_CLK32 32768
27 /* Mainly for compatible to imx common code. */
42 /* PLL supported by i.mx7d */
44 PLL_CORE, /* Core PLL */
45 PLL_SYS, /* System PLL*/
46 PLL_ENET, /* Enet PLL */
47 PLL_AUDIO, /* Audio PLL */
48 PLL_VIDEO, /* Video PLL*/
49 PLL_DDR, /* Dram PLL */
50 PLL_USB, /* USB PLL, fixed at 480MHZ */
53 /* clk src for clock root gen */
57 PLL_ARM_MAIN_800M_CLK,
59 PLL_SYS_MAIN_480M_CLK,
60 PLL_SYS_MAIN_240M_CLK,
61 PLL_SYS_MAIN_120M_CLK,
62 PLL_SYS_PFD0_392M_CLK,
63 PLL_SYS_PFD0_196M_CLK,
64 PLL_SYS_PFD1_332M_CLK,
65 PLL_SYS_PFD1_166M_CLK,
66 PLL_SYS_PFD2_270M_CLK,
67 PLL_SYS_PFD2_135M_CLK,
74 PLL_ENET_MAIN_500M_CLK,
75 PLL_ENET_MAIN_250M_CLK,
76 PLL_ENET_MAIN_125M_CLK,
77 PLL_ENET_MAIN_100M_CLK,
78 PLL_ENET_MAIN_50M_CLK,
79 PLL_ENET_MAIN_40M_CLK,
80 PLL_ENET_MAIN_25M_CLK,
82 PLL_DRAM_MAIN_1066M_CLK,
83 PLL_DRAM_MAIN_533M_CLK,
88 PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */
102 enum clk_root_index {
106 MAIN_AXI_CLK_ROOT = 16,
107 DISP_AXI_CLK_ROOT = 17,
108 ENET_AXI_CLK_ROOT = 18,
109 NAND_USDHC_BUS_CLK_ROOT = 19,
111 DRAM_PHYM_CLK_ROOT = 48,
113 DRAM_PHYM_ALT_CLK_ROOT = 64,
114 DRAM_ALT_CLK_ROOT = 65,
115 USB_HSIC_CLK_ROOT = 66,
116 PCIE_CTRL_CLK_ROOT = 67,
117 PCIE_PHY_CLK_ROOT = 68,
118 EPDC_PIXEL_CLK_ROOT = 69,
119 LCDIF_PIXEL_CLK_ROOT = 70,
120 MIPI_DSI_EXTSER_CLK_ROOT = 71,
121 MIPI_CSI_WARP_CLK_ROOT = 72,
122 MIPI_DPHY_REF_CLK_ROOT = 73,
127 ENET1_REF_CLK_ROOT = 78,
128 ENET1_TIME_CLK_ROOT = 79,
129 ENET2_REF_CLK_ROOT = 80,
130 ENET2_TIME_CLK_ROOT = 81,
131 ENET_PHY_REF_CLK_ROOT = 82,
135 USDHC1_CLK_ROOT = 86,
136 USDHC2_CLK_ROOT = 87,
137 USDHC3_CLK_ROOT = 88,
149 UART6_CLK_ROOT = 100,
150 UART7_CLK_ROOT = 101,
151 ECSPI1_CLK_ROOT = 102,
152 ECSPI2_CLK_ROOT = 103,
153 ECSPI3_CLK_ROOT = 104,
154 ECSPI4_CLK_ROOT = 105,
159 FLEXTIMER1_CLK_ROOT = 110,
160 FLEXTIMER2_CLK_ROOT = 111,
167 TRACE_CLK_ROOT = 118,
169 CSI_MCLK_CLK_ROOT = 120,
170 AUDIO_MCLK_CLK_ROOT = 121,
171 WRCLK_CLK_ROOT = 122,
178 struct clk_root_setting {
179 enum clk_root_index root;
186 enum clk_ccgr_index {
190 CCGR_SIM_DISPLAY = 5,
216 CCGR_QOS_DISPMIX = 43,
217 CCGR_QOS_MEGAMIX = 44,
235 CCGR_MIPI_MEM_PHY = 102,
289 CCGR_IOMUX_LPSR = 169,
296 /* Clock root channel */
301 CCM_DRAM_PHYM_CHANNEL,
306 #include <asm/arch/clock_slice.h>
309 * entry: the clock root index
311 * src_mux: each entry corresponding to the clock src, detailed info in CCM RM
313 struct clk_root_map {
314 enum clk_root_index entry;
315 enum clk_root_type type;
325 u32 get_root_clk(enum clk_root_index clock_id);
326 u32 mxc_get_clock(enum mxc_clock clk);
327 u32 imx_get_uartclk(void);
328 u32 imx_get_fecclk(void);
329 void clock_init(void);
330 #ifdef CONFIG_SYS_I2C_MXC
331 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
333 #ifdef CONFIG_FEC_MXC
334 int set_clk_enet(enum enet_freq type);
336 int set_clk_qspi(void);
337 int set_clk_nand(void);
338 #ifdef CONFIG_MXC_OCOTP
339 void enable_ocotp_clk(unsigned char enable);
341 void enable_usboh3_clk(unsigned char enable);
342 #ifdef CONFIG_SECURE_BOOT
343 void hab_caam_clock_enable(unsigned char enable);
345 void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
346 void enable_thermal_clk(void);