2 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
5 * Peng Fan <Peng.Fan@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef _ASM_ARCH_CLOCK_SLICE_H
11 #define _ASM_ARCH_CLOCK_SLICE_H
14 CLK_ROOT_PRE_DIV1 = 0,
25 CLK_ROOT_POST_DIV1 = 0,
92 CLK_ROOT_AUTO_DIV1 = 0,
99 int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src);
100 int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
101 int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div);
102 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
103 int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div);
104 int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div);
105 int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
107 int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
109 int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
110 int clock_set_target_val(enum clk_root_index clock_id, u32 val);
111 int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
112 enum root_post_div post_div, enum clk_root_src clock_src);
113 int clock_root_enabled(enum clk_root_index clock_id);
115 int clock_enable(enum clk_ccgr_index index, bool enable);