1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
6 #ifndef __ASM_ARCH_MX7_IMX_REGS_H__
7 #define __ASM_ARCH_MX7_IMX_REGS_H__
11 #define ROM_SW_INFO_ADDR 0x000001E8
12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x00017FFF
14 #define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR
15 #define CAAM_ARB_BASE_ADDR 0x00100000
16 #define CAAM_ARB_END_ADDR 0x00107FFF
17 #define GIC400_ARB_BASE_ADDR 0x31000000
18 #define GIC400_ARB_END_ADDR 0x31007FFF
19 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
20 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
21 #define M4_BOOTROM_BASE_ADDR 0x00180000
23 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
24 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
25 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
27 /* GPV - PL301 configuration ports */
28 #define GPV0_BASE_ADDR 0x32000000
29 #define GPV1_BASE_ADDR 0x32100000
30 #define GPV2_BASE_ADDR 0x32200000
31 #define GPV3_BASE_ADDR 0x32300000
32 #define GPV4_BASE_ADDR 0x32400000
33 #define GPV5_BASE_ADDR 0x32500000
34 #define GPV6_BASE_ADDR 0x32600000
35 #define GPV7_BASE_ADDR 0x32700000
37 #define OCRAM_ARB_BASE_ADDR 0x00900000
38 #define OCRAM_ARB_END_ADDR 0x0091FFFF
39 #define OCRAM_EPDC_BASE_ADDR 0x00920000
40 #define OCRAM_EPDC_END_ADDR 0x0093FFFF
41 #define OCRAM_PXP_BASE_ADDR 0x00940000
42 #define OCRAM_PXP_END_ADDR 0x00947FFF
43 #define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR
44 #define IRAM_SIZE 0x00020000
46 #define AIPS1_ARB_BASE_ADDR 0x30000000
47 #define AIPS1_ARB_END_ADDR 0x303FFFFF
48 #define AIPS2_ARB_BASE_ADDR 0x30400000
49 #define AIPS2_ARB_END_ADDR 0x307FFFFF
50 #define AIPS3_ARB_BASE_ADDR 0x30800000
51 #define AIPS3_ARB_END_ADDR 0x30BFFFFF
53 #define WEIM_ARB_BASE_ADDR 0x28000000
54 #define WEIM_ARB_END_ADDR 0x2FFFFFFF
56 #define QSPI0_ARB_BASE_ADDR 0x60000000
57 #define QSPI0_ARB_END_ADDR 0x6FFFFFFF
58 #define PCIE_ARB_BASE_ADDR 0x40000000
59 #define PCIE_ARB_END_ADDR 0x4FFFFFFF
60 #define PCIE_REG_BASE_ADDR 0x33800000
61 #define PCIE_REG_END_ADDR 0x33803FFF
63 #define MMDC0_ARB_BASE_ADDR 0x80000000
64 #define MMDC0_ARB_END_ADDR 0xBFFFFFFF
65 #define MMDC1_ARB_BASE_ADDR 0xC0000000
66 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
68 /* Cortex-A9 MPCore private memory region */
69 #define ARM_PERIPHBASE 0x31000000
70 #define SCU_BASE_ADDR ARM_PERIPHBASE
71 #define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200)
72 #define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600)
75 /* Defines for Blocks connected via AIPS (SkyBlue) */
76 #define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
77 #define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
78 #define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
80 /* DAP base-address */
81 #define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR
83 /* AIPS_TZ#1- On Platform */
84 #define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000)
85 /* AIPS_TZ#1- Off Platform */
86 #define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000)
88 #define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR
89 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000)
90 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000)
91 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000)
92 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000)
93 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000)
94 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000)
95 #define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000)
96 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000)
97 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000)
98 #define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000)
99 #define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000)
100 #define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000)
101 #define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000)
102 #define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR
103 #define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000)
104 #define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000)
105 #define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000)
106 #define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000)
107 #define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000)
108 #define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000)
109 #define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR
110 #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000)
111 #define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000)
112 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000)
113 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000)
114 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000)
115 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000)
116 #define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000)
117 #define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000)
118 #define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000)
119 #define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000)
120 #define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000)
122 /* AIPS_TZ#2- On Platform */
123 #define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000)
124 /* AIPS_TZ#2- Off Platform */
125 #define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000)
126 #define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000)
127 #define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000)
128 #define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000)
129 #define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000)
130 #define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000)
131 #define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000)
132 #define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000)
133 #define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000)
134 #define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000)
135 #define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000)
136 #define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000)
137 #define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000)
138 #define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000)
139 #define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000)
140 #define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR
141 #define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000)
142 #define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000)
143 #define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000)
144 #define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000)
145 #define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000)
146 #define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000)
147 #define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000)
148 #define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000)
149 #define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000)
150 #define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000)
151 #define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000)
152 #define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000)
154 /* AIPS_TZ#3 - Global enable (0) */
155 #define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000)
156 #define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000)
157 #define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000)
158 #define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000)
159 #define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000)
160 #define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000)
161 #define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000)
162 #define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000)
163 #define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000)
164 #define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000)
165 #define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000)
167 /* AIPS_TZ#3- On Platform */
168 #define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000)
169 /* AIPS_TZ#3- Off Platform */
170 #define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000)
171 #define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR
172 #define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000)
173 #define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000)
174 #define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000)
175 #define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000)
176 #define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000)
177 #define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000)
178 #define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000)
179 #define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000)
180 #define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000)
181 #define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000)
182 #define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000)
183 #define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000)
184 #define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000)
185 #define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000)
186 #define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000)
187 #define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000)
188 #define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000)
189 #define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000)
190 #define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000)
191 #define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
192 #define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
193 #define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
194 #define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
195 #define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000)
196 #define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000)
197 #define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000)
198 #define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000)
199 #define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000)
201 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
202 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
203 #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
205 #define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR
206 #define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR
208 #define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR
209 #define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR
211 #define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR
212 #define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR
213 #define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR
214 #define RDC_BASE_ADDR RDC_IPS_BASE_ADDR
216 #define FEC_QUIRK_ENET_MAC
217 #define SNVS_LPGPR 0x68
218 #define CONFIG_SYS_FSL_SEC_OFFSET 0
219 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
220 CONFIG_SYS_FSL_SEC_OFFSET)
221 #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
222 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
223 CONFIG_SYS_FSL_JR0_OFFSET)
224 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
225 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
226 #include <asm/mach-imx/regs-lcdif.h>
227 #include <asm/types.h>
229 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
231 /* System Reset Controller (SRC) */
266 #define src_base ((struct src *)SRC_BASE_ADDR)
268 #define SRC_M4_REG_OFFSET 0xC
269 #define SRC_M4C_NON_SCLR_RST_OFFSET 0
270 #define SRC_M4C_NON_SCLR_RST_MASK BIT(0)
271 #define SRC_M4_ENABLE_OFFSET 3
272 #define SRC_M4_ENABLE_MASK BIT(3)
274 #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1
275 #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1)
277 /* GPR0 Bit Fields */
278 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u
279 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0
280 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u
281 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1
282 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u
283 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2
284 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u
285 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3
286 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u
287 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4
288 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u
289 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5
290 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u
291 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6
292 #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7)
293 #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7
294 /* GPR1 Bit Fields */
295 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u
296 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0
297 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u
298 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1
299 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK)
300 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u
301 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3
302 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u
303 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4
304 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK)
305 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u
306 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6
307 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u
308 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7
309 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK)
310 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u
311 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9
312 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u
313 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10
314 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK)
315 #define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u
316 #define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12
317 #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
318 #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13
319 #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u
320 #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14
321 #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u
322 #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15
323 #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u
324 #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16
325 #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u
326 #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17
327 #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u
328 #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18
329 #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u
330 #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22
331 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u
332 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23
333 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u
334 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28
335 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK)
336 #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u
337 #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30
338 /* GPR2 Bit Fields */
339 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u
340 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0
341 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u
342 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1
343 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u
344 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2
345 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u
346 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3
347 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u
348 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4
349 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u
350 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5
351 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u
352 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6
353 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u
354 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7
355 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u
356 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8
357 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u
358 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9
359 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u
360 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10
361 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u
362 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11
363 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u
364 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12
365 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u
366 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13
367 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u
368 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14
369 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u
370 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15
371 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u
372 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16
373 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK)
374 #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u
375 #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24
376 #define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u
377 #define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25
378 #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u
379 #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26
380 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u
381 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27
382 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u
383 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28
384 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u
385 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29
386 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u
387 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30
388 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u
389 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31
390 /* GPR3 Bit Fields */
391 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u
392 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0
393 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u
394 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1
395 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u
396 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2
397 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u
398 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3
399 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u
400 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4
401 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u
402 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5
403 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u
404 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6
405 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u
406 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7
407 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u
408 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8
409 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u
410 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9
411 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u
412 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10
413 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u
414 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11
415 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u
416 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12
417 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u
418 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13
419 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u
420 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14
421 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u
422 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15
423 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u
424 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16
425 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u
426 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17
427 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u
428 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18
429 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u
430 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19
431 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u
432 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20
433 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u
434 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21
435 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u
436 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22
437 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u
438 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23
439 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u
440 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24
441 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u
442 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25
443 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u
444 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26
445 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u
446 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27
447 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u
448 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28
449 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u
450 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29
451 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u
452 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30
453 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u
454 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31
455 /* GPR4 Bit Fields */
456 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u
457 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0
458 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u
459 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1
460 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u
461 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2
462 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u
463 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3
464 #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u
465 #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4
466 #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u
467 #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5
468 #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u
469 #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6
470 #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u
471 #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7
472 #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u
473 #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16
474 #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u
475 #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17
476 #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u
477 #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18
478 #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u
479 #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19
480 #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u
481 #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20
482 #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u
483 #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21
484 #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u
485 #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22
486 #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u
487 #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23
488 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u
489 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25
490 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK)
491 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u
492 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27
493 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK)
494 /* GPR5 Bit Fields */
495 #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u
496 #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4
497 #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u
498 #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5
499 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u
500 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6
501 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u
502 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7
503 #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u
504 #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12
505 #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u
506 #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19
507 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u
508 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20
509 #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u
510 #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21
511 #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u
512 #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22
513 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u
514 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24
515 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u
516 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25
517 #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u
518 #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26
519 #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u
520 #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27
521 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u
522 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28
523 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u
524 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29
525 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u
526 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30
527 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u
528 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31
529 /* GPR6 Bit Fields */
530 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u
531 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0
532 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u
533 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1
534 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u
535 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2
536 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u
537 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3
538 /* GPR7 Bit Fields */
539 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u
540 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0
541 #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u
542 #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1
543 #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u
544 #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2
545 #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u
546 #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3
547 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u
548 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4
549 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK)
550 #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u
551 #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6
552 #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u
553 #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7
554 #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u
555 #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8
556 #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u
557 #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9
558 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u
559 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10
560 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK)
561 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u
562 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12
563 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u
564 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13
565 /* GPR8 Bit Fields */
566 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u
567 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3
568 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK)
569 #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u
570 #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8
571 /* GPR9 Bit Fields */
572 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u
573 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0
574 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu
575 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1
576 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK)
577 /* GPR10 Bit Fields */
578 #define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u
579 #define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0
580 #define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u
581 #define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1
582 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u
583 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2
584 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u
585 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3
586 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u
587 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4
588 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK)
589 /* GPR11 Bit Fields */
590 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u
591 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0
592 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu
593 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1
594 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK)
595 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u
596 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6
597 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u
598 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7
599 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK)
600 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u
601 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10
602 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u
603 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11
604 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK)
605 /* GPR12 Bit Fields */
606 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u
607 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0
608 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u
609 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1
610 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u
611 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3
612 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u
613 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4
614 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u
615 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5
616 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u
617 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12
618 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK)
619 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u
620 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17
621 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
622 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u
623 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21
624 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK)
625 /* GPR13 Bit Fields */
626 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u
627 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0
628 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u
629 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1
630 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u
631 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2
632 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u
633 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3
634 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u
635 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4
636 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u
637 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5
638 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u
639 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6
640 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u
641 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7
642 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u
643 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8
644 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u
645 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9
646 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u
647 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10
648 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u
649 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11
650 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u
651 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12
652 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u
653 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13
654 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u
655 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14
656 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u
657 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15
658 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u
659 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16
660 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK)
661 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u
662 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24
663 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK)
664 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u
665 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28
666 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u
667 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29
668 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u
669 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30
670 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u
671 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31
672 /* GPR14 Bit Fields */
673 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u
674 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0
675 #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u
676 #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1
677 /* GPR15 Bit Fields */
678 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u
679 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0
680 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u
681 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1
682 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu
683 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2
684 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK)
685 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u
686 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16
687 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK)
688 /* GPR16 Bit Fields */
689 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u
690 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0
691 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK)
692 #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u
693 #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2
694 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u
695 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3
696 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u
697 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4
698 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u
699 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5
700 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u
701 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6
702 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK)
703 #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u
704 #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10
705 #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u
706 #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11
707 #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u
708 #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12
709 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u
710 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13
711 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK)
712 #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u
713 #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16
714 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u
715 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17
716 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u
717 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19
718 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK)
719 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u
720 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21
721 #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u
722 #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22
723 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u
724 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23
725 /* GPR17 Bit Fields */
726 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu
727 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0
728 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK)
729 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u
730 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8
731 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK)
732 /* GPR18 Bit Fields */
733 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u
734 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0
735 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK)
736 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u
737 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3
738 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK)
739 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u
740 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5
741 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK)
742 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u
743 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8
744 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK)
745 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u
746 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14
747 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u
748 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16
749 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK)
750 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u
751 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24
752 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK)
753 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u
754 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26
755 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u
756 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27
757 #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u
758 #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28
759 #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u
760 #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29
761 /* GPR19 Bit Fields */
762 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u
763 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0
764 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u
765 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8
766 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK)
767 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u
768 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16
769 #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u
770 #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17
771 /* GPR20 Bit Fields */
772 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu
773 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0
774 #define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK)
775 #define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u
776 #define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8
777 #define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK)
778 #define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u
779 #define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16
780 #define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK)
781 #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u
782 #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24
783 #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u
784 #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25
785 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u
786 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27
787 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK)
788 /* GPR21 Bit Fields */
789 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u
790 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0
791 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK)
792 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u
793 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3
794 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK)
795 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u
796 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6
797 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK)
798 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u
799 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9
800 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK)
801 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u
802 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12
803 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK)
804 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u
805 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15
806 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK)
807 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u
808 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18
809 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u
810 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19
811 /* GPR22 Bit Fields */
812 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u
813 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16
814 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK)
815 #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u
816 #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24
817 #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u
818 #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25
819 #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u
820 #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26
821 #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u
822 #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27
823 #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u
824 #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28
825 #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u
826 #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29
827 #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u
828 #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31
830 #define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4)
831 #define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4)
832 #define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4)
836 /* mux and pad registers */
839 struct iomuxc_gpr_base_regs {
840 u32 gpr[23]; /* 0x000 */
843 /* ECSPI registers */
856 * CSPI register definitions
859 #define MXC_CSPICTRL_EN (1 << 0)
860 #define MXC_CSPICTRL_MODE (1 << 1)
861 #define MXC_CSPICTRL_XCH (1 << 2)
862 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
863 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
864 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
865 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
866 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
867 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
868 #define MXC_CSPICTRL_MAXBITS 0xfff
869 #define MXC_CSPICTRL_TC (1 << 7)
870 #define MXC_CSPICTRL_RXOVF (1 << 6)
871 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
872 #define MAX_SPI_BYTES 32
874 /* Bit position inside CTRL register to be associated with SS */
875 #define MXC_CSPICTRL_CHAN 18
877 /* Bit position inside CON register to be associated with SS */
878 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
879 #define MXC_CSPICON_POL 4 /* SCLK polarity */
880 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
881 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
883 #define MXC_SPI_BASE_ADDRESSES \
889 #define CSU_INIT_SEC_LEVEL0 0x00FF00FF
890 #define CSU_NUM_REGS 64
930 struct fuse_bank { /* offset 0x400 */
935 struct fuse_bank0_regs {
946 struct fuse_bank1_regs {
957 struct fuse_bank2_regs {
968 struct fuse_bank3_regs {
979 struct fuse_bank8_regs {
990 struct fuse_bank9_regs {
1011 u16 wcr; /* Control */
1012 u16 wsr; /* Service */
1013 u16 wrsr; /* Reset Status */
1014 u16 wicr; /* Interrupt Control */
1015 u16 wmcr; /* Miscellaneous Control */
1018 struct dbg_monitor_regs {
1019 u32 ctrl[4]; /* Control */
1020 u32 master_en[4]; /* Master enable */
1021 u32 irq[4]; /* IRQ */
1022 u32 trap_addr_low[4]; /* Trap address low */
1023 u32 trap_addr_high[4]; /* Trap address high */
1024 u32 trap_id[4]; /* Trap ID */
1025 u32 snvs_addr[4]; /* SNVS address */
1026 u32 snvs_data[4]; /* SNVS data */
1027 u32 snvs_info[4]; /* SNVS info */
1028 u32 version[4]; /* Version */
1032 u32 vir; /* Version information */
1034 u32 stat; /* Status */
1035 u32 intctrl; /* Interrupt and Control */
1036 u32 intstat; /* Interrupt Status */
1038 u32 mda[27]; /* Master Domain Assignment */
1040 u32 pdap[118]; /* Peripheral Domain Access Permissions */
1043 u32 mrsa; /* Memory Region Start Address */
1044 u32 mrea; /* Memory Region End Address */
1045 u32 mrc; /* Memory Region Control */
1046 u32 mrvs; /* Memory Region Violation Status */
1050 struct rdc_sema_regs {
1051 u8 gate[64]; /* Gate */
1052 u16 rstgt; /* Reset Gate */
1055 #define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR
1057 #define LCDIF_CTRL_SFTRST (1 << 31)
1058 #define LCDIF_CTRL_CLKGATE (1 << 30)
1059 #define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
1060 #define LCDIF_CTRL_READ_WRITEB (1 << 28)
1061 #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
1062 #define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
1063 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
1064 #define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
1065 #define LCDIF_CTRL_DVI_MODE (1 << 20)
1066 #define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
1067 #define LCDIF_CTRL_VSYNC_MODE (1 << 18)
1068 #define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
1069 #define LCDIF_CTRL_DATA_SELECT (1 << 16)
1070 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
1071 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
1072 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
1073 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
1074 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
1075 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
1076 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
1077 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
1078 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
1079 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
1080 #define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
1081 #define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
1082 #define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
1083 #define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
1084 #define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
1085 #define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
1086 #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
1087 #define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
1088 #define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
1089 #define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
1090 #define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
1091 #define LCDIF_CTRL_RUN (1 << 0)
1093 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
1094 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
1095 #define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
1096 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
1097 #define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
1098 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
1099 #define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
1100 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
1101 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
1102 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
1103 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
1104 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
1105 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
1106 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
1107 #define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
1108 #define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
1109 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
1110 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
1111 #define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
1112 #define LCDIF_CTRL1_MODE86 (1 << 1)
1113 #define LCDIF_CTRL1_RESET (1 << 0)
1115 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
1116 #define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
1117 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
1118 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
1119 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
1120 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
1121 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
1122 #define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
1123 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
1124 #define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
1125 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
1126 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
1127 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
1128 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
1129 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
1130 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
1131 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
1132 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
1133 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
1134 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
1135 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
1136 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
1137 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
1138 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
1139 #define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
1140 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
1141 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
1142 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
1143 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
1144 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
1145 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
1147 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
1148 #define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
1149 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
1150 #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
1152 #define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
1153 #define LCDIF_CUR_BUF_ADDR_OFFSET 0
1155 #define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
1156 #define LCDIF_NEXT_BUF_ADDR_OFFSET 0
1158 #define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
1159 #define LCDIF_TIMING_CMD_HOLD_OFFSET 24
1160 #define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
1161 #define LCDIF_TIMING_CMD_SETUP_OFFSET 16
1162 #define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
1163 #define LCDIF_TIMING_DATA_HOLD_OFFSET 8
1164 #define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
1165 #define LCDIF_TIMING_DATA_SETUP_OFFSET 0
1167 #define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
1168 #define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
1169 #define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
1170 #define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
1171 #define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
1172 #define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
1173 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
1174 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
1175 #define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
1176 #define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
1177 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
1178 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
1180 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
1181 #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
1183 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
1184 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
1185 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
1186 #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
1188 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
1189 #define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
1190 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
1191 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
1192 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
1193 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
1195 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
1196 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
1197 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
1198 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
1199 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
1202 extern void check_cpu_temperature(void);
1204 extern void pcie_power_up(void);
1205 extern void pcie_power_off(void);
1207 /* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
1208 * If boot from the other mode, USB0_PWD will keep reset value
1210 #define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \
1211 readl(USBOTG2_IPS_BASE_ADDR + 0x158))
1212 #define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)
1214 struct bootrom_sw_info {
1216 u8 boot_dev_instance;
1226 #endif /* __ASSEMBLER__*/
1227 #endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */