2 * DDR controller registers of the i.MX7 architecture
4 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
6 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef __ASM_ARCH_MX7_DDR_H__
12 #define __ASM_ARCH_MX7_DDR_H__
14 /* DDRC Registers (DDRC_IPS_BASE_ADDR) */
16 u32 mstr; /* 0x0000 */
18 u32 rfshtmg; /* 0x0064 */
20 u32 init0; /* 0x00d0 */
21 u32 init1; /* 0x00d4 */
23 u32 init3; /* 0x00dc */
24 u32 init4; /* 0x00e0 */
25 u32 init5; /* 0x00e4 */
27 u32 rankctl; /* 0x00f4 */
29 u32 dramtmg0; /* 0x0100 */
30 u32 dramtmg1; /* 0x0104 */
31 u32 dramtmg2; /* 0x0108 */
32 u32 dramtmg3; /* 0x010c */
33 u32 dramtmg4; /* 0x0110 */
34 u32 dramtmg5; /* 0x0114 */
36 u32 dramtmg8; /* 0x0120 */
38 u32 zqctl0; /* 0x0180 */
40 u32 dfitmg0; /* 0x0190 */
41 u32 dfitmg1; /* 0x0194 */
43 u32 dfiupd0; /* 0x01a0 */
44 u32 dfiupd1; /* 0x01a4 */
45 u32 dfiupd2; /* 0x01a8 */
47 u32 addrmap0; /* 0x0200 */
48 u32 addrmap1; /* 0x0204 */
49 u32 addrmap2; /* 0x0208 */
50 u32 addrmap3; /* 0x020c */
51 u32 addrmap4; /* 0x0210 */
52 u32 addrmap5; /* 0x0214 */
53 u32 addrmap6; /* 0x0218 */
55 u32 odtcfg; /* 0x0240 */
56 u32 odtmap; /* 0x0244 */
59 /* DDRC_MSTR fields */
60 #define MSTR_DATA_BUS_WIDTH_MASK 0x3 << 12
61 #define MSTR_DATA_BUS_WIDTH_SHIFT 12
62 #define MSTR_DATA_ACTIVE_RANKS_MASK 0xf << 24
63 #define MSTR_DATA_ACTIVE_RANKS_SHIFT 24
64 /* DDRC_ADDRMAP1 fields */
65 #define ADDRMAP1_BANK_B0_MASK 0x1f << 0
66 #define ADDRMAP1_BANK_B0_SHIFT 0
67 #define ADDRMAP1_BANK_B1_MASK 0x1f << 8
68 #define ADDRMAP1_BANK_B1_SHIFT 8
69 #define ADDRMAP1_BANK_B2_MASK 0x1f << 16
70 #define ADDRMAP1_BANK_B2_SHIFT 16
71 /* DDRC_ADDRMAP2 fields */
72 #define ADDRMAP2_COL_B2_MASK 0xF << 0
73 #define ADDRMAP2_COL_B2_SHIFT 0
74 #define ADDRMAP2_COL_B3_MASK 0xF << 8
75 #define ADDRMAP2_COL_B3_SHIFT 8
76 #define ADDRMAP2_COL_B4_MASK 0xF << 16
77 #define ADDRMAP2_COL_B4_SHIFT 16
78 #define ADDRMAP2_COL_B5_MASK 0xF << 24
79 #define ADDRMAP2_COL_B5_SHIFT 24
80 /* DDRC_ADDRMAP3 fields */
81 #define ADDRMAP3_COL_B6_MASK 0xF << 0
82 #define ADDRMAP3_COL_B6_SHIFT 0
83 #define ADDRMAP3_COL_B7_MASK 0xF << 8
84 #define ADDRMAP3_COL_B7_SHIFT 8
85 #define ADDRMAP3_COL_B8_MASK 0xF << 16
86 #define ADDRMAP3_COL_B8_SHIFT 16
87 #define ADDRMAP3_COL_B9_MASK 0xF << 24
88 #define ADDRMAP3_COL_B9_SHIFT 24
89 /* DDRC_ADDRMAP4 fields */
90 #define ADDRMAP4_COL_B10_MASK 0xF << 0
91 #define ADDRMAP4_COL_B10_SHIFT 0
92 #define ADDRMAP4_COL_B11_MASK 0xF << 8
93 #define ADDRMAP4_COL_B11_SHIFT 8
94 /* DDRC_ADDRMAP5 fields */
95 #define ADDRMAP5_ROW_B0_MASK 0xF << 0
96 #define ADDRMAP5_ROW_B0_SHIFT 0
97 #define ADDRMAP5_ROW_B1_MASK 0xF << 8
98 #define ADDRMAP5_ROW_B1_SHIFT 8
99 #define ADDRMAP5_ROW_B2_10_MASK 0xF << 16
100 #define ADDRMAP5_ROW_B2_10_SHIFT 16
101 #define ADDRMAP5_ROW_B11_MASK 0xF << 24
102 #define ADDRMAP5_ROW_B11_SHIFT 24
103 /* DDRC_ADDRMAP6 fields */
104 #define ADDRMAP6_ROW_B12_MASK 0xF << 0
105 #define ADDRMAP6_ROW_B12_SHIFT 0
106 #define ADDRMAP6_ROW_B13_MASK 0xF << 8
107 #define ADDRMAP6_ROW_B13_SHIFT 8
108 #define ADDRMAP6_ROW_B14_MASK 0xF << 16
109 #define ADDRMAP6_ROW_B14_SHIFT 16
110 #define ADDRMAP6_ROW_B15_MASK 0xF << 24
111 #define ADDRMAP6_ROW_B15_SHIFT 24
113 /* DDRC_MP Registers */
114 #define DDRC_MP_BASE_ADDR (DDRC_IPS_BASE_ADDR + 0x03fc)
117 u32 pctrl_0; /* 0x0094 */
120 /* DDR_PHY registers */
122 u32 phy_con0; /* 0x0000 */
123 u32 phy_con1; /* 0x0004 */
125 u32 phy_con4; /* 0x0010 */
127 u32 offset_lp_con0; /* 0x0018 */
129 u32 offset_rd_con0; /* 0x0020 */
131 u32 offset_wr_con0; /* 0x0030 */
133 u32 cmd_sdll_con0; /* 0x0050 */
135 u32 drvds_con0; /* 0x009c */
137 u32 mdll_con0; /* 0x00b0 */
139 u32 zq_con0; /* 0x00c0 */
142 #define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK BIT(24)
144 #define MX7_CAL_VAL_MAX 5
145 /* Calibration parameters */
146 struct mx7_calibration {
147 int num_val; /* Number of calibration values */
148 u32 values[MX7_CAL_VAL_MAX]; /* calibration values */
151 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
152 struct ddr_phy *ddr_phy_regs_val,
153 struct mx7_calibration *calib_param);
155 #endif /*__ASM_ARCH_MX7_DDR_H__ */