1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * DDR controller registers of the i.MX7 architecture
5 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
7 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
10 #ifndef __ASM_ARCH_MX7_DDR_H__
11 #define __ASM_ARCH_MX7_DDR_H__
13 /* DDRC Registers (DDRC_IPS_BASE_ADDR) */
15 u32 mstr; /* 0x0000 */
17 u32 rfshtmg; /* 0x0064 */
19 u32 init0; /* 0x00d0 */
20 u32 init1; /* 0x00d4 */
22 u32 init3; /* 0x00dc */
23 u32 init4; /* 0x00e0 */
24 u32 init5; /* 0x00e4 */
26 u32 rankctl; /* 0x00f4 */
28 u32 dramtmg0; /* 0x0100 */
29 u32 dramtmg1; /* 0x0104 */
30 u32 dramtmg2; /* 0x0108 */
31 u32 dramtmg3; /* 0x010c */
32 u32 dramtmg4; /* 0x0110 */
33 u32 dramtmg5; /* 0x0114 */
35 u32 dramtmg8; /* 0x0120 */
37 u32 zqctl0; /* 0x0180 */
39 u32 dfitmg0; /* 0x0190 */
40 u32 dfitmg1; /* 0x0194 */
42 u32 dfiupd0; /* 0x01a0 */
43 u32 dfiupd1; /* 0x01a4 */
44 u32 dfiupd2; /* 0x01a8 */
46 u32 addrmap0; /* 0x0200 */
47 u32 addrmap1; /* 0x0204 */
48 u32 addrmap2; /* 0x0208 */
49 u32 addrmap3; /* 0x020c */
50 u32 addrmap4; /* 0x0210 */
51 u32 addrmap5; /* 0x0214 */
52 u32 addrmap6; /* 0x0218 */
54 u32 odtcfg; /* 0x0240 */
55 u32 odtmap; /* 0x0244 */
58 /* DDRC_MSTR fields */
59 #define MSTR_DATA_BUS_WIDTH_MASK 0x3 << 12
60 #define MSTR_DATA_BUS_WIDTH_SHIFT 12
61 #define MSTR_DATA_ACTIVE_RANKS_MASK 0xf << 24
62 #define MSTR_DATA_ACTIVE_RANKS_SHIFT 24
63 /* DDRC_ADDRMAP1 fields */
64 #define ADDRMAP1_BANK_B0_MASK 0x1f << 0
65 #define ADDRMAP1_BANK_B0_SHIFT 0
66 #define ADDRMAP1_BANK_B1_MASK 0x1f << 8
67 #define ADDRMAP1_BANK_B1_SHIFT 8
68 #define ADDRMAP1_BANK_B2_MASK 0x1f << 16
69 #define ADDRMAP1_BANK_B2_SHIFT 16
70 /* DDRC_ADDRMAP2 fields */
71 #define ADDRMAP2_COL_B2_MASK 0xF << 0
72 #define ADDRMAP2_COL_B2_SHIFT 0
73 #define ADDRMAP2_COL_B3_MASK 0xF << 8
74 #define ADDRMAP2_COL_B3_SHIFT 8
75 #define ADDRMAP2_COL_B4_MASK 0xF << 16
76 #define ADDRMAP2_COL_B4_SHIFT 16
77 #define ADDRMAP2_COL_B5_MASK 0xF << 24
78 #define ADDRMAP2_COL_B5_SHIFT 24
79 /* DDRC_ADDRMAP3 fields */
80 #define ADDRMAP3_COL_B6_MASK 0xF << 0
81 #define ADDRMAP3_COL_B6_SHIFT 0
82 #define ADDRMAP3_COL_B7_MASK 0xF << 8
83 #define ADDRMAP3_COL_B7_SHIFT 8
84 #define ADDRMAP3_COL_B8_MASK 0xF << 16
85 #define ADDRMAP3_COL_B8_SHIFT 16
86 #define ADDRMAP3_COL_B9_MASK 0xF << 24
87 #define ADDRMAP3_COL_B9_SHIFT 24
88 /* DDRC_ADDRMAP4 fields */
89 #define ADDRMAP4_COL_B10_MASK 0xF << 0
90 #define ADDRMAP4_COL_B10_SHIFT 0
91 #define ADDRMAP4_COL_B11_MASK 0xF << 8
92 #define ADDRMAP4_COL_B11_SHIFT 8
93 /* DDRC_ADDRMAP5 fields */
94 #define ADDRMAP5_ROW_B0_MASK 0xF << 0
95 #define ADDRMAP5_ROW_B0_SHIFT 0
96 #define ADDRMAP5_ROW_B1_MASK 0xF << 8
97 #define ADDRMAP5_ROW_B1_SHIFT 8
98 #define ADDRMAP5_ROW_B2_10_MASK 0xF << 16
99 #define ADDRMAP5_ROW_B2_10_SHIFT 16
100 #define ADDRMAP5_ROW_B11_MASK 0xF << 24
101 #define ADDRMAP5_ROW_B11_SHIFT 24
102 /* DDRC_ADDRMAP6 fields */
103 #define ADDRMAP6_ROW_B12_MASK 0xF << 0
104 #define ADDRMAP6_ROW_B12_SHIFT 0
105 #define ADDRMAP6_ROW_B13_MASK 0xF << 8
106 #define ADDRMAP6_ROW_B13_SHIFT 8
107 #define ADDRMAP6_ROW_B14_MASK 0xF << 16
108 #define ADDRMAP6_ROW_B14_SHIFT 16
109 #define ADDRMAP6_ROW_B15_MASK 0xF << 24
110 #define ADDRMAP6_ROW_B15_SHIFT 24
112 /* DDRC_MP Registers */
113 #define DDRC_MP_BASE_ADDR (DDRC_IPS_BASE_ADDR + 0x03fc)
116 u32 pctrl_0; /* 0x0094 */
119 /* DDR_PHY registers */
121 u32 phy_con0; /* 0x0000 */
122 u32 phy_con1; /* 0x0004 */
124 u32 phy_con4; /* 0x0010 */
126 u32 offset_lp_con0; /* 0x0018 */
128 u32 offset_rd_con0; /* 0x0020 */
130 u32 offset_wr_con0; /* 0x0030 */
132 u32 cmd_sdll_con0; /* 0x0050 */
134 u32 drvds_con0; /* 0x009c */
136 u32 mdll_con0; /* 0x00b0 */
138 u32 zq_con0; /* 0x00c0 */
141 #define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK BIT(24)
143 #define MX7_CAL_VAL_MAX 5
144 /* Calibration parameters */
145 struct mx7_calibration {
146 int num_val; /* Number of calibration values */
147 u32 values[MX7_CAL_VAL_MAX]; /* calibration values */
150 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
151 struct ddr_phy *ddr_phy_regs_val,
152 struct mx7_calibration *calib_param);
154 #endif /*__ASM_ARCH_MX7_DDR_H__ */