2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _MX7ULP_REGS_H_
8 #define _MX7ULP_REGS_H_
10 #include <linux/sizes.h>
12 #define CAAM_SEC_SRAM_BASE (0x26000000)
13 #define CAAM_SEC_SRAM_SIZE (SZ_32K)
14 #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1)
16 #define OCRAM_0_BASE (0x2F000000)
17 #define OCRAM_0_SIZE (SZ_128K)
18 #define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1)
20 #define OCRAM_1_BASE (0x2F020000)
21 #define OCRAM_1_SIZE (SZ_128K)
22 #define OCRAM_1_END (OCRAM_1_BASE + OCRAM_1_SIZE - 1)
24 #define TCML_BASE (0x1FFD0000)
25 #define TCMU_BASE (0x20000000)
27 #define AIPS3_BASE (0x40800000UL)
28 #define AIPS3_SLOT_SIZE (SZ_64K)
29 #define AIPS2_BASE (0x40000000UL)
30 #define AIPS2_SLOT_SIZE (SZ_64K)
31 #define AIPS1_BASE (0x41080000UL)
32 #define AIPS1_SLOT_SIZE (SZ_4K)
33 #define AIPS0_BASE (0x41000000UL)
34 #define AIPS0_SLOT_SIZE (SZ_4K)
35 #define IOMUXC0_AIPS0_SLOT (61)
36 #define WDG0_AIPS0_SLOT (37)
37 #define WDG1_AIPS2_SLOT (61)
38 #define WDG2_AIPS2_SLOT (67)
39 #define WDG0_PCC0_SLOT (37)
40 #define IOMUXC1_AIPS3_SLOT (44)
41 #define CMC0_AIPS1_SLOT (36)
42 #define CMC1_AIPS2_SLOT (65)
43 #define SCG0_AIPS0_SLOT (39)
44 #define PCC0_AIPS0_SLOT (38)
45 #define PCC1_AIPS1_SLOT (50)
46 #define PCC2_AIPS2_SLOT (63)
47 #define PCC3_AIPS3_SLOT (51)
48 #define SCG1_AIPS2_SLOT (62)
49 #define SIM0_AIPS1_SLOT (35)
50 #define SIM1_AIPS1_SLOT (48)
51 #define USBOTG0_AIPS2_SLOT (51)
52 #define USBOTG1_AIPS2_SLOT (52)
53 #define USBPHY_AIPS2_SLOT (53)
54 #define USDHC0_AIPS2_SLOT (55)
55 #define USDHC1_AIPS2_SLOT (56)
56 #define RGPIO2P0_AIPS0_SLOT (15)
57 #define RGPIO2P1_AIPS2_SLOT (15)
58 #define IOMUXC0_AIPS0_SLOT (61)
59 #define OCOTP_CTRL_AIPS1_SLOT (38)
60 #define OCOTP_CTRL_PCC1_SLOT (38)
61 #define SIM1_PCC1_SLOT (48)
62 #define MMDC0_AIPS3_SLOT (43)
63 #define IOMUXC_DDR_AIPS3_SLOT (45)
65 #define LPI2C0_AIPS0_SLOT (51)
66 #define LPI2C1_AIPS0_SLOT (52)
67 #define LPI2C2_AIPS0_SLOT (53)
68 #define LPI2C3_AIPS0_SLOT (54)
69 #define LPI2C4_AIPS2_SLOT (43)
70 #define LPI2C5_AIPS2_SLOT (44)
71 #define LPI2C6_AIPS3_SLOT (36)
72 #define LPI2C7_AIPS3_SLOT (37)
74 #define LPUART0_PCC0_SLOT (58)
75 #define LPUART1_PCC0_SLOT (59)
76 #define LPUART2_PCC1_SLOT (43)
77 #define LPUART3_PCC1_SLOT (44)
78 #define LPUART0_AIPS0_SLOT (58)
79 #define LPUART1_AIPS0_SLOT (59)
80 #define LPUART2_AIPS1_SLOT (43)
81 #define LPUART3_AIPS1_SLOT (44)
82 #define LPUART4_AIPS2_SLOT (45)
83 #define LPUART5_AIPS2_SLOT (46)
84 #define LPUART6_AIPS3_SLOT (38)
85 #define LPUART7_AIPS3_SLOT (39)
87 #define CORE_B_ROM_SIZE (SZ_32K + SZ_64K)
88 #define CORE_B_ROM_BASE (0x00000000)
90 #define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE
91 #define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE
92 #define IRAM_BASE_ADDR OCRAM_0_BASE
93 #define IRAM_SIZE (SZ_128K + SZ_128K)
95 #define IOMUXC_PCR_MUX_ALT0 (0<<8)
96 #define IOMUXC_PCR_MUX_ALT1 (1<<8)
97 #define IOMUXC_PCR_MUX_ALT2 (2<<8)
98 #define IOMUXC_PCR_MUX_ALT3 (3<<8)
99 #define IOMUXC_PCR_MUX_ALT4 (4<<8)
100 #define IOMUXC_PCR_MUX_ALT5 (5<<8)
101 #define IOMUXC_PCR_MUX_ALT6 (6<<8)
102 #define IOMUXC_PCR_MUX_ALT7 (7<<8)
103 #define IOMUXC_PCR_MUX_ALT8 (8<<8)
104 #define IOMUXC_PCR_MUX_ALT9 (9<<8)
105 #define IOMUXC_PCR_MUX_ALT10 (10<<8)
106 #define IOMUXC_PCR_MUX_ALT11 (11<<8)
107 #define IOMUXC_PCR_MUX_ALT12 (12<<8)
108 #define IOMUXC_PCR_MUX_ALT13 (13<<8)
109 #define IOMUXC_PCR_MUX_ALT14 (14<<8)
110 #define IOMUXC_PCR_MUX_ALT15 (15<<8)
112 #define IOMUXC_PSMI_IMUX_ALT0 (0x0)
113 #define IOMUXC_PSMI_IMUX_ALT1 (0x1)
114 #define IOMUXC_PSMI_IMUX_ALT2 (0x2)
115 #define IOMUXC_PSMI_IMUX_ALT3 (0x3)
116 #define IOMUXC_PSMI_IMUX_ALT4 (0x4)
117 #define IOMUXC_PSMI_IMUX_ALT5 (0x5)
118 #define IOMUXC_PSMI_IMUX_ALT6 (0x6)
119 #define IOMUXC_PSMI_IMUX_ALT7 (0x7)
122 #define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8)
123 #define SIM_SOPT1_PMIC_STBY_REQ (1<<2)
124 #define SIM_SOPT1_A7_SW_RESET (1<<0)
126 #define IOMUXC_PCR_MUX_ALT_SHIFT (8)
127 #define IOMUXC_PCR_MUX_ALT_MASK (0xF00)
128 #define IOMUXC_PSMI_IMUX_ALT_SHIFT (0)
130 #define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT)))
131 #define IOMUXC1_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT)))
132 #define WDG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT)))
133 #define WDG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT)))
134 #define WDG2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT)))
135 #define SCG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT)))
136 #define SCG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT)))
137 #define PCC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT)))
138 #define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT)))
139 #define PCC2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT)))
140 #define PCC3_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT)))
141 #define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT)))
142 #define PSMI0_RBASE ((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */
143 #define CMC0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT)))
144 #define CMC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT)))
145 #define OCOTP_BASE_ADDR ((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT)))
146 #define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT)))
147 #define SIM1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT)))
148 #define MMDC0_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT)))
150 #define USBOTG0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT)))
151 #define USBOTG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT)))
152 #define USBPHY_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT)))
153 #define USB_PHY0_BASE_ADDR USBPHY_RBASE
154 #define USB_BASE_ADDR USBOTG0_RBASE
156 #define LPI2C1_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT)))
157 #define LPI2C2_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT)))
158 #define LPI2C3_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT)))
159 #define LPI2C4_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT)))
160 #define LPI2C5_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT)))
161 #define LPI2C6_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT)))
162 #define LPI2C7_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT)))
163 #define LPI2C8_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT)))
165 #define LPUART0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT)))
166 #define LPUART1_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT)))
167 #define LPUART2_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT)))
168 #define LPUART3_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT)))
169 #define LPUART4_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT)))
170 #define LPUART5_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT)))
171 #define LPUART6_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT)))
172 #define LPUART7_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT)))
174 #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT)))
175 #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT)))
177 #define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT)))
178 #define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT)))
180 #define WDG0_PCC_REG (PCC0_RBASE + (4 * WDG0_PCC0_SLOT))
181 #define WDG1_PCC_REG (PCC2_RBASE + (4 * WDG1_PCC2_SLOT))
182 #define CMC0_SRS (CMC0_RBASE + 0x20)
183 #define CMC0_SSRS (CMC0_RBASE + 0x28)
184 #define CMC1_SRS (CMC1_RBASE + 0x20)
185 #define CMC1_SSRS (CMC1_RBASE + 0x28)
187 #define IOMUXC0_PCR0 (IOMUXC0_RBASE + (4 * 0))
188 #define IOMUXC0_PCR1 (IOMUXC0_RBASE + (4 * 1))
189 #define IOMUXC0_PCR2 (IOMUXC0_RBASE + (4 * 2))
190 #define IOMUXC0_PCR3 (IOMUXC0_RBASE + (4 * 3))
191 #define IOMUXC0_PSMI62 (PSMI0_RBASE + (4 * 62))
192 #define IOMUXC0_PSMI63 (PSMI0_RBASE + (4 * 63))
193 #define IOMUXC0_PSMI64 (PSMI0_RBASE + (4 * 64))
195 #define SCG_CSR (SCG0_RBASE + 0x010)
196 #define SCG_RCCR (SCG0_RBASE + 0x014)
197 #define SCG_VCCR (SCG0_RBASE + 0x018)
198 #define SCG_HCCR (SCG0_RBASE + 0x01c)
200 #define LPUART0_PCC_REG (PCC0_RBASE + (4 * LPUART0_PCC0_SLOT))
201 #define LPUART1_PCC_REG (PCC0_RBASE + (4 * LPUART1_PCC0_SLOT))
202 #define LPUART2_PCC_REG (PCC1_RBASE + (4 * LPUART2_PCC1_SLOT))
203 #define LPUART3_PCC_REG (PCC1_RBASE + (4 * LPUART3_PCC1_SLOT))
204 #define LPUART4_PCC_REG (PCC2_RBASE + (4 * LPUART4_PCC2_SLOT))
205 #define LPUART5_PCC_REG (PCC2_RBASE + (4 * LPUART5_PCC2_SLOT))
206 #define LPUART6_PCC_REG (PCC3_RBASE + (4 * LPUART6_PCC3_SLOT))
207 #define LPUART7_PCC_REG (PCC3_RBASE + (4 * LPUART7_PCC3_SLOT))
209 #define USDHC0_PCC_REG (PCC2_RBASE + (4 * USDHC0_PCC2_SLOT))
210 #define USDHC1_PCC_REG (PCC2_RBASE + (4 * USDHC1_PCC2_SLOT))
212 #define SIM1_PCC_REG (PCC1_RBASE + (4 * SIM1_PCC1_SLOT))
213 #define SCG1_PCC_REG (PCC2_RBASE + (4 * SCG1_PCC2_SLOT))
215 #define OCOTP_CTRL_PCC_REG (PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT))
217 #define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT)))
218 #define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT))
220 #define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
221 #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))
222 #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34)))
223 #define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35)))
226 #define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0)))
227 #define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1)))
228 #define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2)))
229 #define IOMUXC_DPCR_DDR_DQ3 ((IOMUXC_DDR_RBASE + (4 * 3)))
230 #define IOMUXC_DPCR_DDR_DQ4 ((IOMUXC_DDR_RBASE + (4 * 4)))
231 #define IOMUXC_DPCR_DDR_DQ5 ((IOMUXC_DDR_RBASE + (4 * 5)))
232 #define IOMUXC_DPCR_DDR_DQ6 ((IOMUXC_DDR_RBASE + (4 * 6)))
233 #define IOMUXC_DPCR_DDR_DQ7 ((IOMUXC_DDR_RBASE + (4 * 7)))
234 #define IOMUXC_DPCR_DDR_DQ8 ((IOMUXC_DDR_RBASE + (4 * 8)))
235 #define IOMUXC_DPCR_DDR_DQ9 ((IOMUXC_DDR_RBASE + (4 * 9)))
236 #define IOMUXC_DPCR_DDR_DQ10 ((IOMUXC_DDR_RBASE + (4 * 10)))
237 #define IOMUXC_DPCR_DDR_DQ11 ((IOMUXC_DDR_RBASE + (4 * 11)))
238 #define IOMUXC_DPCR_DDR_DQ12 ((IOMUXC_DDR_RBASE + (4 * 12)))
239 #define IOMUXC_DPCR_DDR_DQ13 ((IOMUXC_DDR_RBASE + (4 * 13)))
240 #define IOMUXC_DPCR_DDR_DQ14 ((IOMUXC_DDR_RBASE + (4 * 14)))
241 #define IOMUXC_DPCR_DDR_DQ15 ((IOMUXC_DDR_RBASE + (4 * 15)))
242 #define IOMUXC_DPCR_DDR_DQ16 ((IOMUXC_DDR_RBASE + (4 * 16)))
243 #define IOMUXC_DPCR_DDR_DQ17 ((IOMUXC_DDR_RBASE + (4 * 17)))
244 #define IOMUXC_DPCR_DDR_DQ18 ((IOMUXC_DDR_RBASE + (4 * 18)))
245 #define IOMUXC_DPCR_DDR_DQ19 ((IOMUXC_DDR_RBASE + (4 * 19)))
246 #define IOMUXC_DPCR_DDR_DQ20 ((IOMUXC_DDR_RBASE + (4 * 20)))
247 #define IOMUXC_DPCR_DDR_DQ21 ((IOMUXC_DDR_RBASE + (4 * 21)))
248 #define IOMUXC_DPCR_DDR_DQ22 ((IOMUXC_DDR_RBASE + (4 * 22)))
249 #define IOMUXC_DPCR_DDR_DQ23 ((IOMUXC_DDR_RBASE + (4 * 23)))
250 #define IOMUXC_DPCR_DDR_DQ24 ((IOMUXC_DDR_RBASE + (4 * 24)))
251 #define IOMUXC_DPCR_DDR_DQ25 ((IOMUXC_DDR_RBASE + (4 * 25)))
252 #define IOMUXC_DPCR_DDR_DQ26 ((IOMUXC_DDR_RBASE + (4 * 26)))
253 #define IOMUXC_DPCR_DDR_DQ27 ((IOMUXC_DDR_RBASE + (4 * 27)))
254 #define IOMUXC_DPCR_DDR_DQ28 ((IOMUXC_DDR_RBASE + (4 * 28)))
255 #define IOMUXC_DPCR_DDR_DQ29 ((IOMUXC_DDR_RBASE + (4 * 29)))
256 #define IOMUXC_DPCR_DDR_DQ30 ((IOMUXC_DDR_RBASE + (4 * 30)))
257 #define IOMUXC_DPCR_DDR_DQ31 ((IOMUXC_DDR_RBASE + (4 * 31)))
259 /* Remap the rgpio2p registers addr to driver's addr */
260 #define RGPIO2P_GPIO1_BASE_ADDR RGPIO2P0_RBASE
261 #define RGPIO2P_GPIO2_BASE_ADDR (RGPIO2P0_RBASE + 0x40)
262 #define RGPIO2P_GPIO3_BASE_ADDR (RGPIO2P1_RBASE)
263 #define RGPIO2P_GPIO4_BASE_ADDR (RGPIO2P1_RBASE + 0x40)
264 #define RGPIO2P_GPIO5_BASE_ADDR (RGPIO2P1_RBASE + 0x80)
265 #define RGPIO2P_GPIO6_BASE_ADDR (RGPIO2P1_RBASE + 0xc0)
267 /* MMDC registers addresses */
268 #define MMDC_MDCTL_OFFSET (0x000)
269 #define MMDC_MDPDC_OFFSET (0x004)
270 #define MMDC_MDOTC_OFFSET (0x008)
271 #define MMDC_MDCFG0_OFFSET (0x00C)
272 #define MMDC_MDCFG1_OFFSET (0x010)
273 #define MMDC_MDCFG2_OFFSET (0x014)
274 #define MMDC_MDMISC_OFFSET (0x018)
275 #define MMDC_MDSCR_OFFSET (0x01C)
276 #define MMDC_MDREF_OFFSET (0x020)
277 #define MMDC_MDRWD_OFFSET (0x02C)
278 #define MMDC_MDOR_OFFSET (0x030)
279 #define MMDC_MDMRR_OFFSET (0x034)
280 #define MMDC_MDCFG3LP_OFFSET (0x038)
281 #define MMDC_MDMR4_OFFSET (0x03C)
282 #define MMDC_MDASP_OFFSET (0x040)
284 #define MMDC_MAARCR_OFFSET (0x400)
285 #define MMDC_MAPSR_OFFSET (0x404)
286 #define MMDC_MAEXIDR0_OFFSET (0x408)
287 #define MMDC_MAEXIDR1_OFFSET (0x40C)
288 #define MMDC_MADPCR0_OFFSET (0x410)
289 #define MMDC_MADPCR1_OFFSET (0x414)
290 #define MMDC_MADPSR0_OFFSET (0x418)
291 #define MMDC_MADPSR1_OFFSET (0x41C)
292 #define MMDC_MADPSR2_OFFSET (0x420)
293 #define MMDC_MADPSR3_OFFSET (0x424)
294 #define MMDC_MADPSR4_OFFSET (0x428)
295 #define MMDC_MADPSR5_OFFSET (0x42C)
296 #define MMDC_MASBS0_OFFSET (0x430)
297 #define MMDC_MASBS1_OFFSET (0x434)
298 #define MMDC_MAGENP_OFFSET (0x440)
300 #define MMDC_MPZQHWCTRL_OFFSET (0x800)
301 #define MMDC_MPZQSWCTRL_OFFSET (0x804)
302 #define MMDC_MPWLGCR_OFFSET (0x808)
303 #define MMDC_MPWLDECTRL0_OFFSET (0x80C)
304 #define MMDC_MPWLDECTRL1_OFFSET (0x810)
305 #define MMDC_MPWLDLST_OFFSET (0x814)
306 #define MMDC_MPODTCTRL_OFFSET (0x818)
307 #define MMDC_MPREDQBY0DL_OFFSET (0x81C)
308 #define MMDC_MPREDQBY1DL_OFFSET (0x820)
309 #define MMDC_MPREDQBY2DL_OFFSET (0x824)
310 #define MMDC_MPREDQBY3DL_OFFSET (0x828)
311 #define MMDC_MPWRDQBY0DL_OFFSET (0x82C)
312 #define MMDC_MPWRDQBY1DL_OFFSET (0x830)
313 #define MMDC_MPWRDQBY2DL_OFFSET (0x834)
314 #define MMDC_MPWRDQBY3DL_OFFSET (0x838)
315 #define MMDC_MPDGCTRL0_OFFSET (0x83C)
316 #define MMDC_MPDGCTRL1_OFFSET (0x840)
317 #define MMDC_MPDGDLST_OFFSET (0x844)
318 #define MMDC_MPRDDLCTL_OFFSET (0x848)
319 #define MMDC_MPRDDLST_OFFSET (0x84C)
320 #define MMDC_MPWRDLCTL_OFFSET (0x850)
321 #define MMDC_MPWRDLST_OFFSET (0x854)
322 #define MMDC_MPSDCTRL_OFFSET (0x858)
323 #define MMDC_MPZQLP2CTL_OFFSET (0x85C)
324 #define MMDC_MPRDDLHWCTL_OFFSET (0x860)
325 #define MMDC_MPWRDLHWCTL_OFFSET (0x864)
326 #define MMDC_MPRDDLHWST0_OFFSET (0x868)
327 #define MMDC_MPRDDLHWST1_OFFSET (0x86C)
328 #define MMDC_MPWRDLHWST0_OFFSET (0x870)
329 #define MMDC_MPWRDLHWST1_OFFSET (0x874)
330 #define MMDC_MPWLHWERR_OFFSET (0x878)
331 #define MMDC_MPDGHWST0_OFFSET (0x87C)
332 #define MMDC_MPDGHWST1_OFFSET (0x880)
333 #define MMDC_MPDGHWST2_OFFSET (0x884)
334 #define MMDC_MPDGHWST3_OFFSET (0x888)
335 #define MMDC_MPPDCMPR1_OFFSET (0x88C)
336 #define MMDC_MPPDCMPR2_OFFSET (0x890)
337 #define MMDC_MPSWDAR_OFFSET (0x894)
338 #define MMDC_MPSWDRDR0_OFFSET (0x898)
339 #define MMDC_MPSWDRDR1_OFFSET (0x89C)
340 #define MMDC_MPSWDRDR2_OFFSET (0x8A0)
341 #define MMDC_MPSWDRDR3_OFFSET (0x8A4)
342 #define MMDC_MPSWDRDR4_OFFSET (0x8A8)
343 #define MMDC_MPSWDRDR5_OFFSET (0x8AC)
344 #define MMDC_MPSWDRDR6_OFFSET (0x8B0)
345 #define MMDC_MPSWDRDR7_OFFSET (0x8B4)
346 #define MMDC_MPMUR_OFFSET (0x8B8)
347 #define MMDC_MPWRCADL_OFFSET (0x8BC)
348 #define MMDC_MPDCCR_OFFSET (0x8C0)
349 #define MMDC_MPBC_OFFSET (0x8C4)
350 #define MMDC_MPSWDRAR_OFFSET (0x8C8)
352 /* First MMDC invalid IPS address */
353 #define MMDC_IPS_ILL_ADDR_START_OFFSET (0x8CC)
354 #define MMDC_REGS_BASE MMDC0_RBASE
356 #define MMDC_MDCTL ((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET))
357 #define MMDC_MDPDC ((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET))
358 #define MMDC_MDOTC ((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET))
359 #define MMDC_MDCFG0 ((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET))
360 #define MMDC_MDCFG1 ((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET))
361 #define MMDC_MDCFG2 ((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET))
362 #define MMDC_MDMISC ((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET))
363 #define MMDC_MDSCR ((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET))
364 #define MMDC_MDREF ((MMDC_REGS_BASE + MMDC_MDREF_OFFSET))
365 #define MMDC_MDRWD ((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET))
366 #define MMDC_MDOR ((MMDC_REGS_BASE + MMDC_MDOR_OFFSET))
367 #define MMDC_MDMRR ((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET))
368 #define MMDC_MDCFG3LP ((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET))
369 #define MMDC_MDMR4 ((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET))
370 #define MMDC_MDASP ((MMDC_REGS_BASE + MMDC_MDASP_OFFSET))
372 #define MMDC_MAARCR ((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET))
373 #define MMDC_MAPSR ((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET))
374 #define MMDC_MAEXIDR0 ((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET))
375 #define MMDC_MAEXIDR1 ((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET))
376 #define MMDC_MADPCR0 ((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET))
377 #define MMDC_MADPCR1 ((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET))
378 #define MMDC_MADPSR0 ((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET))
379 #define MMDC_MADPSR1 ((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET))
380 #define MMDC_MADPSR2 ((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET))
381 #define MMDC_MADPSR3 ((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET))
382 #define MMDC_MADPSR4 ((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET))
383 #define MMDC_MADPSR5 ((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET))
384 #define MMDC_MASBS0 ((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET))
385 #define MMDC_MASBS1 ((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET))
386 #define MMDC_MAGENP ((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET))
388 #define MMDC_MPZQHWCTRL ((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET))
389 #define MMDC_MPZQSWCTRL ((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET))
390 #define MMDC_MPWLGCR ((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET))
391 #define MMDC_MPWLDECTRL0 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET))
392 #define MMDC_MPWLDECTRL1 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET))
393 #define MMDC_MPWLDLST ((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET))
394 #define MMDC_MPODTCTRL ((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET))
395 #define MMDC_MPREDQBY0DL ((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET))
396 #define MMDC_MPREDQBY1DL ((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET))
397 #define MMDC_MPREDQBY2DL ((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET))
398 #define MMDC_MPREDQBY3DL ((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET))
399 #define MMDC_MPWRDQBY0DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET))
400 #define MMDC_MPWRDQBY1DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET))
401 #define MMDC_MPWRDQBY2DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET))
402 #define MMDC_MPWRDQBY3DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET))
403 #define MMDC_MPDGCTRL0 ((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET))
404 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET))
405 #define MMDC_MPDGDLST ((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET))
406 #define MMDC_MPRDDLCTL ((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET))
407 #define MMDC_MPRDDLST ((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET))
408 #define MMDC_MPWRDLCTL ((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET))
409 #define MMDC_MPWRDLST ((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET))
410 #define MMDC_MPSDCTRL ((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET))
411 #define MMDC_MPZQLP2CTL ((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET))
412 #define MMDC_MPRDDLHWCTL ((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET))
413 #define MMDC_MPWRDLHWCTL ((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET))
414 #define MMDC_MPRDDLHWST0 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET))
415 #define MMDC_MPRDDLHWST1 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET))
416 #define MMDC_MPWRDLHWST0 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET))
417 #define MMDC_MPWRDLHWST1 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET))
418 #define MMDC_MPWLHWERR ((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET))
419 #define MMDC_MPDGHWST0 ((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET))
420 #define MMDC_MPDGHWST1 ((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET))
421 #define MMDC_MPDGHWST2 ((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET))
422 #define MMDC_MPDGHWST3 ((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET))
423 #define MMDC_MPPDCMPR1 ((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET))
424 #define MMDC_MPPDCMPR2 ((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET))
425 #define MMDC_MPSWDAR ((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET))
426 #define MMDC_MPSWDRDR0 ((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET))
427 #define MMDC_MPSWDRDR1 ((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET))
428 #define MMDC_MPSWDRDR2 ((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET))
429 #define MMDC_MPSWDRDR3 ((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET))
430 #define MMDC_MPSWDRDR4 ((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET))
431 #define MMDC_MPSWDRDR5 ((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET))
432 #define MMDC_MPSWDRDR6 ((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET))
433 #define MMDC_MPSWDRDR7 ((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET))
434 #define MMDC_MPMUR ((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET))
435 #define MMDC_MPWRCADL ((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET))
436 #define MMDC_MPDCCR ((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET))
437 #define MMDC_MPBC ((MMDC_REGS_BASE + MMDC_MPBC_OFFSET))
438 #define MMDC_MPSWDRAR ((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET))
440 /* MMDC registers bit defines */
441 #define MMDC_MDCTL_SDE_0 (31)
442 #define MMDC_MDCTL_SDE_1 (30)
443 #define MMDC_MDCTL_ROW (24)
444 #define MMDC_MDCTL_COL (20)
445 #define MMDC_MDCTL_BL (19)
446 #define MMDC_MDCTL_DSIZ (16)
449 #define MMDC_MDMISC_CS0_RDY (31)
450 #define MMDC_MDMISC_CS1_RDY (30)
451 #define MMDC_MDMISC_CK1_DEL (22)
452 #define MMDC_MDMISC_CK1_GATING (21)
453 #define MMDC_MDMISC_CALIB_PER_CS (20)
454 #define MMDC_MDMISC_ADDR_MIRROR (19)
455 #define MMDC_MDMISC_LHD (18)
456 #define MMDC_MDMISC_WALAT (16)
457 #define MMDC_MDMISC_BI (12)
458 #define MMDC_MDMISC_LPDDR2_S (11)
459 #define MMDC_MDMISC_MIF3_MODE (9)
460 #define MMDC_MDMISC_RALAT (6)
461 #define MMDC_MDMISC_DDR_4_BANK (5)
462 #define MMDC_MDMISC_DDR_TYPE (3)
463 #define MMDC_MDMISC_RST (1)
466 #define MMDC_MPWLGCR_WL_HW_ERR (8)
469 #define MMDC_MDSCR_CMD_ADDR_MSB (24)
470 #define MMDC_MDSCR_MR_OP (24)
471 #define MMDC_MDSCR_CMD_ADDR_LSB (16)
472 #define MMDC_MDSCR_MR_ADDR (16)
473 #define MMDC_MDSCR_CON_REQ (15)
474 #define MMDC_MDSCR_CON_ACK (14)
475 #define MMDC_MDSCR_MRR_READ_DATA_VALID (10)
476 #define MMDC_MDSCR_WL_EN (9)
477 #define MMDC_MDSCR_CMD (4)
478 #define MMDC_MDSCR_CMD_CS (3)
479 #define MMDC_MDSCR_CMD_BA (0)
482 #define MMDC_MPZQHWCTRL_ZQ_HW_FOR (16)
483 #define MMDC_MPZQHWCTRL_ZQ_MODE (0)
486 #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP (16)
487 #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL (13)
488 #define MMDC_MPZQSWCTRL_ZQ_SW_PD (12)
489 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL (7)
490 #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL (2)
491 #define MMDC_MPZQSWCTRL_ZQ_SW_RES (1)
492 #define MMDC_MPZQSWCTRL_ZQ_SW_FOR (0)
495 #define MMDC_MPDGCTRL0_RST_RD_FIFO (31)
496 #define MMDC_MPDGCTRL0_DG_CMP_CYC (30)
497 #define MMDC_MPDGCTRL0_DG_DIS (29)
498 #define MMDC_MPDGCTRL0_HW_DG_EN (28)
499 #define MMDC_MPDGCTRL0_HW_DG_ERR (12)
502 #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC (5)
503 #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN (4)
504 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR (0)
507 #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC (5)
508 #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN (4)
509 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR (0)
512 #define MMDC_MPSWDAR_TEST_DUMMY_EN (6)
513 #define MMDC_MPSWDAR_SW_DUM_CMP3 (5)
514 #define MMDC_MPSWDAR_SW_DUM_CMP2 (4)
515 #define MMDC_MPSWDAR_SW_DUM_CMP1 (3)
516 #define MMDC_MPSWDAR_SW_DUM_CMP0 (2)
517 #define MMDC_MPSWDAR_SW_DUMMY_RD (1)
518 #define MMDC_MPSWDAR_SW_DUMMY_WR (0)
521 #define MMDC_MADPCR0_SBS (9)
522 #define MMDC_MADPCR0_SBS_EN (8)
525 #define MMDC_MASBS1_SBS_VLD (0)
526 #define MMDC_MASBS1_SBS_TYPE (1)
529 #define MMDC_MDREF_REF_CNT (16)
530 #define MMDC_MDREF_REF_SEL (14)
531 #define MMDC_MDREF_REFR (11)
532 #define MMDC_MDREF_START_REF (0)
535 #define MMDC_MPWLGCR_HW_WL_EN (0)
538 #define MMDC_MPBC_BIST_DM_LP_EN (0)
539 #define MMDC_MPBC_BIST_CA0_LP_EN (1)
540 #define MMDC_MPBC_BIST_DQ0_LP_EN (3)
541 #define MMDC_MPBC_BIST_DQ1_LP_EN (4)
542 #define MMDC_MPBC_BIST_DQ2_LP_EN (5)
543 #define MMDC_MPBC_BIST_DQ3_LP_EN (6)
546 #define MMDC_MPMUR_FRC_MSR (11)
549 #define MMDC_MPODTCTRL_ODT_RD_ACT_EN (3)
550 #define MMDC_MPODTCTRL_ODT_RD_PAS_EN (2)
551 #define MMDC_MPODTCTRL_ODT_WR_ACT_EN (1)
552 #define MMDC_MPODTCTRL_ODT_WR_PAS_EN (0)
555 #define MMDC_MAPSR_DVACK (25)
556 #define MMDC_MAPSR_LPACK (24)
557 #define MMDC_MAPSR_DVFS (21)
558 #define MMDC_MAPSR_LPMD (20)
561 #define MMDC_MAARCR_ARCR_EXC_ERR_EN (28)
564 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS (24)
565 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL (16)
566 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT (0)
569 #define MMDC_MDCFG3LP_tRC_LP (16)
570 #define MMDC_MDCFG3LP_tRCD_LP (8)
571 #define MMDC_MDCFG3LP_tRPpb_LP (4)
572 #define MMDC_MDCFG3LP_tRPab_LP (0)
575 #define MMDC_MDOR_tXPR (16)
576 #define MMDC_MDOR_SDE_to_RST (8)
577 #define MMDC_MDOR_RST_to_CKE (0)
580 #define MMDC_MDCFG0_tRFC (24)
581 #define MMDC_MDCFG0_tXS (16)
582 #define MMDC_MDCFG0_tXP (13)
583 #define MMDC_MDCFG0_tXPDLL (9)
584 #define MMDC_MDCFG0_tFAW (4)
585 #define MMDC_MDCFG0_tCL (0)
588 #define MMDC_MDCFG1_tRCD (29)
589 #define MMDC_MDCFG1_tRP (26)
590 #define MMDC_MDCFG1_tRC (21)
591 #define MMDC_MDCFG1_tRAS (16)
592 #define MMDC_MDCFG1_tRPA (15)
593 #define MMDC_MDCFG1_tWR (9)
594 #define MMDC_MDCFG1_tMRD (5)
595 #define MMDC_MDCFG1_tCWL (0)
598 #define MMDC_MDCFG2_tDLLK (16)
599 #define MMDC_MDCFG2_tRTP (6)
600 #define MMDC_MDCFG2_tWTR (3)
601 #define MMDC_MDCFG2_tRRD (0)
604 #define MMDC_MDRWD_tDAI (16)
605 #define MMDC_MDRWD_RTW_SAME (12)
606 #define MMDC_MDRWD_WTR_DIFF (9)
607 #define MMDC_MDRWD_WTW_DIFF (6)
608 #define MMDC_MDRWD_RTW_DIFF (3)
609 #define MMDC_MDRWD_RTR_DIFF (0)
612 #define MMDC_MDPDC_PRCT_1 (28)
613 #define MMDC_MDPDC_PRCT_0 (24)
614 #define MMDC_MDPDC_tCKE (16)
615 #define MMDC_MDPDC_PWDT_1 (12)
616 #define MMDC_MDPDC_PWDT_0 (8)
617 #define MMDC_MDPDC_SLOW_PD (7)
618 #define MMDC_MDPDC_BOTH_CS_PD (6)
619 #define MMDC_MDPDC_tCKSRX (3)
620 #define MMDC_MDPDC_tCKSRE (0)
623 #define MMDC_MDASP_CS0_END (0)
626 #define MMDC_MAEXIDR0_EXC_ID_MONITOR1 (16)
627 #define MMDC_MAEXIDR0_EXC_ID_MONITOR0 (0)
630 #define MMDC_MAEXIDR1_EXC_ID_MONITOR3 (16)
631 #define MMDC_MAEXIDR1_EXC_ID_MONITOR2 (0)
634 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3 (24)
635 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2 (16)
636 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1 (8)
637 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0 (0)
640 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3 (24)
641 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2 (16)
642 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1 (8)
643 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0 (0)
646 #define MMDC_MPWRDQBY0DL_WR_DM0_DEL (30)
647 #define MMDC_MPWRDQBY0DL_WR_DQ7_DEL (28)
648 #define MMDC_MPWRDQBY0DL_WR_DQ6_DEL (24)
649 #define MMDC_MPWRDQBY0DL_WR_DQ5_DEL (20)
650 #define MMDC_MPWRDQBY0DL_WR_DQ4_DEL (16)
651 #define MMDC_MPWRDQBY0DL_WR_DQ3_DEL (12)
652 #define MMDC_MPWRDQBY0DL_WR_DQ2_DEL (8)
653 #define MMDC_MPWRDQBY0DL_WR_DQ1_DEL (4)
654 #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL (0)
657 #define MMDC_MPWRDQBY1DL_WR_DM1_DEL (30)
658 #define MMDC_MPWRDQBY1DL_WR_DQ15_DEL (28)
659 #define MMDC_MPWRDQBY1DL_WR_DQ14_DEL (24)
660 #define MMDC_MPWRDQBY1DL_WR_DQ13_DEL (20)
661 #define MMDC_MPWRDQBY1DL_WR_DQ12_DEL (16)
662 #define MMDC_MPWRDQBY1DL_WR_DQ11_DEL (12)
663 #define MMDC_MPWRDQBY1DL_WR_DQ10_DEL (8)
664 #define MMDC_MPWRDQBY1DL_WR_DQ9_DEL (4)
665 #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL (0)
668 #define MMDC_MPWRDQBY2DL_WR_DM2_DEL (30)
669 #define MMDC_MPWRDQBY2DL_WR_DQ23_DEL (28)
670 #define MMDC_MPWRDQBY2DL_WR_DQ22_DEL (24)
671 #define MMDC_MPWRDQBY2DL_WR_DQ21_DEL (20)
672 #define MMDC_MPWRDQBY2DL_WR_DQ20_DEL (16)
673 #define MMDC_MPWRDQBY2DL_WR_DQ19_DEL (12)
674 #define MMDC_MPWRDQBY2DL_WR_DQ18_DEL (8)
675 #define MMDC_MPWRDQBY2DL_WR_DQ17_DEL (4)
676 #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL (0)
679 #define MMDC_MPWRDQBY3DL_WR_DM3_DEL (30)
680 #define MMDC_MPWRDQBY3DL_WR_DQ31_DEL (28)
681 #define MMDC_MPWRDQBY3DL_WR_DQ30_DEL (24)
682 #define MMDC_MPWRDQBY3DL_WR_DQ29_DEL (20)
683 #define MMDC_MPWRDQBY3DL_WR_DQ28_DEL (16)
684 #define MMDC_MPWRDQBY3DL_WR_DQ27_DEL (12)
685 #define MMDC_MPWRDQBY3DL_WR_DQ26_DEL (8)
686 #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL (4)
687 #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL (0)
690 #define MMDC_MDCTL_SDE_0_MASK ((0x1 << MMDC_MDCTL_SDE_0))
691 #define MMDC_MDCTL_SDE_1_MASK ((0x1 << MMDC_MDCTL_SDE_1))
692 #define MMDC_MDCTL_BL_MASK ((0x1 << MMDC_MDCTL_BL))
693 #define MMDC_MDCTL_ROW_MASK ((0x7 << MMDC_MDCTL_ROW))
694 #define MMDC_MDCTL_COL_MASK ((0x7 << MMDC_MDCTL_COL))
695 #define MMDC_MDCTL_DSIZ_MASK ((0x3 << MMDC_MDCTL_DSIZ))
698 #define MMDC_MDMISC_CS0_RDY_MASK ((0x1 << MMDC_MDMISC_CS0_RDY))
699 #define MMDC_MDMISC_CS1_RDY_MASK ((0x1 << MMDC_MDMISC_CS1_RDY))
700 #define MMDC_MDMISC_CK1_DEL_MASK ((0x3 << MMDC_MDMISC_CK1_DEL))
701 #define MMDC_MDMISC_CK1_GATING_MASK ((0x1 << MMDC_MDMISC_CK1_GATING))
702 #define MMDC_MDMISC_CALIB_PER_CS_MASK ((0x1 << MMDC_MDMISC_CALIB_PER_CS))
703 #define MMDC_MDMISC_ADDR_MIRROR_MASK ((0x1 << MMDC_MDMISC_ADDR_MIRROR))
704 #define MMDC_MDMISC_LHD_MASK ((0x1 << MMDC_MDMISC_LHD))
705 #define MMDC_MDMISC_WALAT_MASK ((0x3 << MMDC_MDMISC_WALAT))
706 #define MMDC_MDMISC_BI_MASK ((0x1 << MMDC_MDMISC_BI))
707 #define MMDC_MDMISC_LPDDR2_S_MASK ((0x1 << MMDC_MDMISC_LPDDR2_S))
708 #define MMDC_MDMISC_MIF3_MODE_MASK ((0x3 << MMDC_MDMISC_MIF3_MODE))
709 #define MMDC_MDMISC_RALAT_MASK ((0x7 << MMDC_MDMISC_RALAT))
710 #define MMDC_MDMISC_DDR_4_BANK_MASK ((0x1 << MMDC_MDMISC_DDR_4_BANK))
711 #define MMDC_MDMISC_DDR_TYPE_MASK ((0x3 << MMDC_MDMISC_DDR_TYPE))
712 #define MMDC_MDMISC_RST_MASK ((0x1 << MMDC_MDMISC_RST))
715 #define MMDC_MPWLGCR_WL_HW_ERR_MASK ((0xf << MMDC_MPWLGCR_WL_HW_ERR))
718 #define MMDC_MDSCR_CMD_ADDR_MSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_MSB))
719 #define MMDC_MDSCR_MR_OP_MASK ((0xff << MMDC_MDSCR_MR_OP))
720 #define MMDC_MDSCR_CMD_ADDR_LSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_LSB))
721 #define MMDC_MDSCR_MR_ADDR_MASK ((0xff << MMDC_MDSCR_MR_ADDR))
722 #define MMDC_MDSCR_CON_REQ_MASK ((0x1 << MMDC_MDSCR_CON_REQ))
723 #define MMDC_MDSCR_CON_ACK_MASK ((0x1 << MMDC_MDSCR_CON_ACK))
724 #define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK ((0x1 << MMDC_MDSCR_MRR_READ_DATA_VALID))
725 #define MMDC_MDSCR_WL_EN_MASK ((0x1 << MMDC_MDSCR_WL_EN))
726 #define MMDC_MDSCR_CMD_MASK ((0x7 << MMDC_MDSCR_CMD))
727 #define MMDC_MDSCR_CMD_CS_MASK ((0x1 << MMDC_MDSCR_CMD_CS))
728 #define MMDC_MDSCR_CMD_BA_MASK ((0x7 << MMDC_MDSCR_CMD_BA))
731 #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK ((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR))
732 #define MMDC_MPZQHWCTRL_ZQ_MODE_MASK ((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE))
735 #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK ((0x3 << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP))
736 #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK ((0x1 << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL))
737 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_PD))
738 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL))
739 #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL))
740 #define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_RES))
741 #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_FOR))
744 #define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK ((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO))
745 #define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK ((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC))
746 #define MMDC_MPDGCTRL0_DG_DIS_MASK ((0x1 << MMDC_MPDGCTRL0_DG_DIS))
747 #define MMDC_MPDGCTRL0_HW_DG_EN_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_EN))
748 #define MMDC_MPDGCTRL0_HW_DG_ERR_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR))
751 #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC))
752 #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN))
753 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK ((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR))
756 #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC))
757 #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN))
758 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK ((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR))
761 #define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK ((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN))
762 #define MMDC_MPSWDAR_SW_DUM_CMP3_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3))
763 #define MMDC_MPSWDAR_SW_DUM_CMP2_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2))
764 #define MMDC_MPSWDAR_SW_DUM_CMP1_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1))
765 #define MMDC_MPSWDAR_SW_DUM_CMP0_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0))
766 #define MMDC_MPSWDAR_SW_DUMMY_RD_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD))
767 #define MMDC_MPSWDAR_SW_DUMMY_WR_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR))
770 #define MMDC_MADPCR0_SBS_MASK ((0x1 << MMDC_MADPCR0_SBS))
771 #define MMDC_MADPCR0_SBS_EN_MASK ((0x1 << MMDC_MADPCR0_SBS_EN))
774 #define MMDC_MASBS1_SBS_VLD_MASK ((0x1 << MMDC_MASBS1_SBS_VLD))
775 #define MMDC_MASBS1_SBS_TYPE_MASK ((0x1 << MMDC_MASBS1_SBS_TYPE))
778 #define MMDC_MDREF_REF_CNT_MASK ((0xffff << MMDC_MDREF_REF_CNT))
779 #define MMDC_MDREF_REF_SEL_MASK ((0x3 << MMDC_MDREF_REF_SEL))
780 #define MMDC_MDREF_REFR_MASK ((0x7 << MMDC_MDREF_REFR))
781 #define MMDC_MDREF_START_REF_MASK ((0x1 << MMDC_MDREF_START_REF))
784 #define MMDC_MPWLGCR_HW_WL_EN_MASK ((0x1 << MMDC_MPWLGCR_HW_WL_EN))
787 #define MMDC_MPBC_BIST_DM_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DM_LP_EN))
788 #define MMDC_MPBC_BIST_CA0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_CA0_LP_EN))
789 #define MMDC_MPBC_BIST_DQ0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN))
790 #define MMDC_MPBC_BIST_DQ1_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN))
791 #define MMDC_MPBC_BIST_DQ2_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN))
792 #define MMDC_MPBC_BIST_DQ3_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN))
793 #define MMDC_MPBC_BIST_DQ_LP_EN_MASK ((0xf << MMDC_MPBC_BIST_DQ0_LP_EN))
796 #define MMDC_MPMUR_FRC_MSR_MASK ((0x1 << MMDC_MPMUR_FRC_MSR))
799 #define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN))
800 #define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN))
801 #define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN))
802 #define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN))
805 #define MMDC_MAPSR_DVACK_MASK ((0x1 << MMDC_MAPSR_DVACK))
806 #define MMDC_MAPSR_LPACK_MASK ((0x1 << MMDC_MAPSR_LPACK))
807 #define MMDC_MAPSR_DVFS_MASK ((0x1 << MMDC_MAPSR_DVFS))
808 #define MMDC_MAPSR_LPMD_MASK ((0x1 << MMDC_MAPSR_LPMD))
811 #define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK ((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN))
814 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK ((0x7f << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS))
815 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK ((0xff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL))
816 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK ((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT))
819 #define MMDC_MDCFG3LP_tRC_LP_MASK ((0x3f << MMDC_MDCFG3LP_tRC_LP))
820 #define MMDC_MDCFG3LP_tRCD_LP_MASK ((0xf << MMDC_MDCFG3LP_tRCD_LP))
821 #define MMDC_MDCFG3LP_tRPpb_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPpb_LP))
822 #define MMDC_MDCFG3LP_tRPab_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPab_LP))
825 #define MMDC_MDOR_tXPR_MASK ((0xff << MMDC_MDOR_tXPR))
826 #define MMDC_MDOR_SDE_to_RST_MASK ((0x3f << MMDC_MDOR_SDE_to_RST))
827 #define MMDC_MDOR_RST_to_CKE_MASK ((0x3f << MMDC_MDOR_RST_to_CKE))
830 #define MMDC_MDCFG0_tRFC_MASK ((0xff << MMDC_MDCFG0_tRFC))
831 #define MMDC_MDCFG0_tXS_MASK ((0xff << MMDC_MDCFG0_tXS))
832 #define MMDC_MDCFG0_tXP_MASK ((0x7 << MMDC_MDCFG0_tXP))
833 #define MMDC_MDCFG0_tXPDLL_MASK ((0xf << MMDC_MDCFG0_tXPDLL))
834 #define MMDC_MDCFG0_tFAW_MASK ((0x1f << MMDC_MDCFG0_tFAW))
835 #define MMDC_MDCFG0_tCL_MASK ((0xf << MMDC_MDCFG0_tCL))
838 #define MMDC_MDCFG1_tRCD_MASK ((0x7 << MMDC_MDCFG1_tRCD))
839 #define MMDC_MDCFG1_tRP_MASK ((0x7 << MMDC_MDCFG1_tRP))
840 #define MMDC_MDCFG1_tRC_MASK ((0x1f << MMDC_MDCFG1_tRC))
841 #define MMDC_MDCFG1_tRAS_MASK ((0x1f << MMDC_MDCFG1_tRAS))
842 #define MMDC_MDCFG1_tRPA_MASK ((0x1 << MMDC_MDCFG1_tRPA))
843 #define MMDC_MDCFG1_tWR_MASK ((0x7 << MMDC_MDCFG1_tWR))
844 #define MMDC_MDCFG1_tMRD_MASK ((0xf << MMDC_MDCFG1_tMRD))
845 #define MMDC_MDCFG1_tCWL_MASK ((0x7 << MMDC_MDCFG1_tCWL))
848 #define MMDC_MDCFG2_tDLLK_MASK ((0x1ff << MMDC_MDCFG2_tDLLK))
849 #define MMDC_MDCFG2_tRTP_MASK ((0x7 << MMDC_MDCFG2_tRTP))
850 #define MMDC_MDCFG2_tWTR_MASK ((0x7 << MMDC_MDCFG2_tWTR))
851 #define MMDC_MDCFG2_tRRD_MASK ((0x7 << MMDC_MDCFG2_tRRD))
854 #define MMDC_MDRWD_tDAI_MASK ((0x1fff << MMDC_MDRWD_tDAI))
855 #define MMDC_MDRWD_RTW_SAME_MASK ((0x7 << MMDC_MDRWD_RTW_SAME))
856 #define MMDC_MDRWD_WTR_DIFF_MASK ((0x7 << MMDC_MDRWD_WTR_DIFF))
857 #define MMDC_MDRWD_WTW_DIFF_MASK ((0x7 << MMDC_MDRWD_WTW_DIFF))
858 #define MMDC_MDRWD_RTW_DIFF_MASK ((0x7 << MMDC_MDRWD_RTW_DIFF))
859 #define MMDC_MDRWD_RTR_DIFF_MASK ((0x7 << MMDC_MDRWD_RTR_DIFF))
862 #define MMDC_MDPDC_PRCT_1_MASK ((0x7 << MMDC_MDPDC_PRCT_1))
863 #define MMDC_MDPDC_PRCT_0_MASK ((0x7 << MMDC_MDPDC_PRCT_0))
864 #define MMDC_MDPDC_tCKE_MASK ((0x7 << MMDC_MDPDC_tCKE))
865 #define MMDC_MDPDC_PWDT_1_MASK ((0xf << MMDC_MDPDC_PWDT_1))
866 #define MMDC_MDPDC_PWDT_0_MASK ((0xf << MMDC_MDPDC_PWDT_0))
867 #define MMDC_MDPDC_SLOW_PD_MASK ((0x1 << MMDC_MDPDC_SLOW_PD))
868 #define MMDC_MDPDC_BOTH_CS_PD_MASK ((0x1 << MMDC_MDPDC_BOTH_CS_PD))
869 #define MMDC_MDPDC_tCKSRX_MASK ((0x7 << MMDC_MDPDC_tCKSRX))
870 #define MMDC_MDPDC_tCKSRE_MASK ((0x7 << MMDC_MDPDC_tCKSRE))
873 #define MMDC_MDASP_CS0_END_MASK ((0x7f << MMDC_MDASP_CS0_END))
876 #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1))
877 #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0))
880 #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3))
881 #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2))
884 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3))
885 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2))
886 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1))
887 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0))
890 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3))
891 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2))
892 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1))
893 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0))
896 #define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DM0_DEL))
897 #define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ7_DEL))
898 #define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ6_DEL))
899 #define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ5_DEL))
900 #define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ4_DEL))
901 #define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ3_DEL))
902 #define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ2_DEL))
903 #define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ1_DEL))
904 #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ0_DEL))
907 #define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DM1_DEL))
908 #define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ15_DEL))
909 #define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ14_DEL))
910 #define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ13_DEL))
911 #define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ12_DEL))
912 #define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ11_DEL))
913 #define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ10_DEL))
914 #define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ9_DEL))
915 #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ8_DEL))
918 #define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DM2_DEL))
919 #define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ23_DEL))
920 #define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ22_DEL))
921 #define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ21_DEL))
922 #define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ20_DEL))
923 #define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ19_DEL))
924 #define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ18_DEL))
925 #define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ17_DEL))
926 #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ16_DEL))
929 #define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DM3_DEL))
930 #define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ31_DEL))
931 #define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ30_DEL))
932 #define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ29_DEL))
933 #define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ28_DEL))
934 #define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ27_DEL))
935 #define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ26_DEL))
936 #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL))
937 #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL))
939 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
941 #include <asm/types.h>
975 struct fuse_word mem_repair[8];
984 struct fuse_bank1_regs {
1003 struct fuse_bank2_regs {
1004 struct fuse_word boot[8];
1007 struct fuse_bank3_regs {
1026 struct fuse_bank7_regs {
1045 struct usbphy_regs {
1046 u32 usbphy_pwd; /* 0x000 */
1047 u32 usbphy_pwd_set; /* 0x004 */
1048 u32 usbphy_pwd_clr; /* 0x008 */
1049 u32 usbphy_pwd_tog; /* 0x00c */
1050 u32 usbphy_tx; /* 0x010 */
1051 u32 usbphy_tx_set; /* 0x014 */
1052 u32 usbphy_tx_clr; /* 0x018 */
1053 u32 usbphy_tx_tog; /* 0x01c */
1054 u32 usbphy_rx; /* 0x020 */
1055 u32 usbphy_rx_set; /* 0x024 */
1056 u32 usbphy_rx_clr; /* 0x028 */
1057 u32 usbphy_rx_tog; /* 0x02c */
1058 u32 usbphy_ctrl; /* 0x030 */
1059 u32 usbphy_ctrl_set; /* 0x034 */
1060 u32 usbphy_ctrl_clr; /* 0x038 */
1061 u32 usbphy_ctrl_tog; /* 0x03c */
1062 u32 usbphy_status; /* 0x040 */
1064 u32 usbphy_debug0; /* 0x050 */
1065 u32 usbphy_debug0_set; /* 0x054 */
1066 u32 usbphy_debug0_clr; /* 0x058 */
1067 u32 usbphy_debug0_tog; /* 0x05c */
1069 u32 usbphy_debug1; /* 0x070 */
1070 u32 usbphy_debug1_set; /* 0x074 */
1071 u32 usbphy_debug1_clr; /* 0x078 */
1072 u32 usbphy_debug1_tog; /* 0x07c */
1073 u32 usbphy_version; /* 0x080 */
1075 u32 usb1_pll_480_ctrl; /* 0x0a0 */
1076 u32 usb1_pll_480_ctrl_set; /* 0x0a4 */
1077 u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */
1078 u32 usb1_pll_480_ctrl_tog; /* 0x0ac */
1080 u32 usb1_vbus_detect; /* 0xc0 */
1081 u32 usb1_vbus_detect_set; /* 0xc4 */
1082 u32 usb1_vbus_detect_clr; /* 0xc8 */
1083 u32 usb1_vbus_detect_tog; /* 0xcc */
1084 u32 usb1_vbus_det_stat; /* 0xd0 */
1086 u32 usb1_chrg_detect; /* 0xe0 */
1087 u32 usb1_chrg_detect_set; /* 0xe4 */
1088 u32 usb1_chrg_detect_clr; /* 0xe8 */
1089 u32 usb1_chrg_detect_tog; /* 0xec */
1090 u32 usb1_chrg_det_stat; /* 0xf0 */
1092 u32 usbphy_anactrl; /* 0x100 */
1093 u32 usbphy_anactrl_set; /* 0x104 */
1094 u32 usbphy_anactrl_clr; /* 0x108 */
1095 u32 usbphy_anactrl_tog; /* 0x10c */
1096 u32 usb1_loopback; /* 0x110 */
1097 u32 usb1_loopback_set; /* 0x114 */
1098 u32 usb1_loopback_clr; /* 0x118 */
1099 u32 usb1_loopback_tog; /* 0x11c */
1100 u32 usb1_loopback_hsfscnt; /* 0x120 */
1101 u32 usb1_loopback_hsfscnt_set; /* 0x124 */
1102 u32 usb1_loopback_hsfscnt_clr; /* 0x128 */
1103 u32 usb1_loopback_hsfscnt_tog; /* 0x12c */
1104 u32 usphy_trim_override_en; /* 0x130 */
1105 u32 usphy_trim_override_en_set; /* 0x134 */
1106 u32 usphy_trim_override_en_clr; /* 0x138 */
1107 u32 usphy_trim_override_en_tog; /* 0x13c */
1108 u32 usb1_pfda_ctrl1; /* 0x140 */
1109 u32 usb1_pfda_ctrl1_set; /* 0x144 */
1110 u32 usb1_pfda_ctrl1_clr; /* 0x148 */
1111 u32 usb1_pfda_ctrl1_tog; /* 0x14c */
1115 #define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
1116 #define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140)
1120 #endif /* _MX7ULP_REGS_H_*/