2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARCH_SCG_H
8 #define _ASM_ARCH_SCG_H
12 #ifdef CONFIG_CLK_DEBUG
13 #define clk_debug(fmt, args...) printf(fmt, ##args)
15 #define clk_debug(fmt, args...)
18 #define SCG_CCR_SCS_SHIFT (24)
19 #define SCG_CCR_SCS_MASK ((0xFUL) << SCG_CCR_SCS_SHIFT)
20 #define SCG_CCR_DIVCORE_SHIFT (16)
21 #define SCG_CCR_DIVCORE_MASK ((0xFUL) << SCG_CCR_DIVCORE_SHIFT)
22 #define SCG_CCR_DIVPLAT_SHIFT (12)
23 #define SCG_CCR_DIVPLAT_MASK ((0xFUL) << SCG_CCR_DIVPLAT_SHIFT)
24 #define SCG_CCR_DIVEXT_SHIFT (8)
25 #define SCG_CCR_DIVEXT_MASK ((0xFUL) << SCG_CCR_DIVEXT_SHIFT)
26 #define SCG_CCR_DIVBUS_SHIFT (4)
27 #define SCG_CCR_DIVBUS_MASK ((0xFUL) << SCG_CCR_DIVBUS_SHIFT)
28 #define SCG_CCR_DIVSLOW_SHIFT (0)
29 #define SCG_CCR_DIVSLOW_MASK ((0xFUL) << SCG_CCR_DIVSLOW_SHIFT)
31 /* SCG DDR Clock Control Register */
32 #define SCG_DDRCCR_DDRCS_SHIFT (24)
33 #define SCG_DDRCCR_DDRCS_MASK ((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT)
35 #define SCG_DDRCCR_DDRDIV_SHIFT (0)
36 #define SCG_DDRCCR_DDRDIV_MASK ((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT)
38 /* SCG NIC Clock Control Register */
39 #define SCG_NICCCR_NICCS_SHIFT (28)
40 #define SCG_NICCCR_NICCS_MASK ((0x1UL) << SCG_NICCCR_NICCS_SHIFT)
42 #define SCG_NICCCR_NIC0_DIV_SHIFT (24)
43 #define SCG_NICCCR_NIC0_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT)
45 #define SCG_NICCCR_GPU_DIV_SHIFT (20)
46 #define SCG_NICCCR_GPU_DIV_MASK ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT)
48 #define SCG_NICCCR_NIC1_DIV_SHIFT (16)
49 #define SCG_NICCCR_NIC1_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT)
51 #define SCG_NICCCR_NIC1_DIVEXT_SHIFT (8)
52 #define SCG_NICCCR_NIC1_DIVEXT_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT)
54 #define SCG_NICCCR_NIC1_DIVBUS_SHIFT (4)
55 #define SCG_NICCCR_NIC1_DIVBUS_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
57 /* SCG NIC clock status register */
58 #define SCG_NICCSR_NICCS_SHIFT (28)
59 #define SCG_NICCSR_NICCS_MASK ((0x1UL) << SCG_NICCSR_NICCS_SHIFT)
61 #define SCG_NICCSR_NIC0DIV_SHIFT (24)
62 #define SCG_NICCSR_NIC0DIV_MASK ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT)
63 #define SCG_NICCSR_GPUDIV_SHIFT (20)
64 #define SCG_NICCSR_GPUDIV_MASK ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT)
65 #define SCG_NICCSR_NIC1DIV_SHIFT (16)
66 #define SCG_NICCSR_NIC1DIV_MASK ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT)
67 #define SCG_NICCSR_NIC1EXTDIV_SHIFT (8)
68 #define SCG_NICCSR_NIC1EXTDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT)
69 #define SCG_NICCSR_NIC1BUSDIV_SHIFT (4)
70 #define SCG_NICCSR_NIC1BUSDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT)
72 /* SCG Slow IRC Control Status Register */
73 #define SCG_SIRC_CSR_SIRCVLD_SHIFT (24)
74 #define SCG_SIRC_CSR_SIRCVLD_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT)
76 #define SCG_SIRC_CSR_SIRCEN_SHIFT (0)
77 #define SCG_SIRC_CSR_SIRCEN_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT)
79 /* SCG Slow IRC Configuration Register */
80 #define SCG_SIRCCFG_RANGE_SHIFT (0)
81 #define SCG_SIRCCFG_RANGE_MASK ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
82 #define SCG_SIRCCFG_RANGE_4M ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT)
83 #define SCG_SIRCCFG_RANGE_16M ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
85 /* SCG Slow IRC Divide Register */
86 #define SCG_SIRCDIV_DIV3_SHIFT (16)
87 #define SCG_SIRCDIV_DIV3_MASK ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT)
89 #define SCG_SIRCDIV_DIV2_SHIFT (8)
90 #define SCG_SIRCDIV_DIV2_MASK ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT)
92 #define SCG_SIRCDIV_DIV1_SHIFT (0)
93 #define SCG_SIRCDIV_DIV1_MASK ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT)
95 * FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK
96 * FIRC/SIRC DIV2 ==> xIRC_BUS_CLK
97 * FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK
100 /* SCG Fast IRC Control Status Register */
101 #define SCG_FIRC_CSR_FIRCVLD_SHIFT (24)
102 #define SCG_FIRC_CSR_FIRCVLD_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT)
104 #define SCG_FIRC_CSR_FIRCEN_SHIFT (0)
105 #define SCG_FIRC_CSR_FIRCEN_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT)
107 /* SCG Fast IRC Divide Register */
108 #define SCG_FIRCDIV_DIV3_SHIFT (16)
109 #define SCG_FIRCDIV_DIV3_MASK ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT)
111 #define SCG_FIRCDIV_DIV2_SHIFT (8)
112 #define SCG_FIRCDIV_DIV2_MASK ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT)
114 #define SCG_FIRCDIV_DIV1_SHIFT (0)
115 #define SCG_FIRCDIV_DIV1_MASK ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT)
117 #define SCG_FIRCCFG_RANGE_SHIFT (0)
118 #define SCG_FIRCCFG_RANGE_MASK ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT)
120 #define SCG_FIRCCFG_RANGE_SHIFT (0)
121 #define SCG_FIRCCFG_RANGE_48M ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT)
123 /* SCG System OSC Control Status Register */
124 #define SCG_SOSC_CSR_SOSCVLD_SHIFT (24)
125 #define SCG_SOSC_CSR_SOSCVLD_MASK ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT)
127 /* SCG Fast IRC Divide Register */
128 #define SCG_SOSCDIV_DIV3_SHIFT (16)
129 #define SCG_SOSCDIV_DIV3_MASK ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT)
131 #define SCG_SOSCDIV_DIV2_SHIFT (8)
132 #define SCG_SOSCDIV_DIV2_MASK ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT)
134 #define SCG_SOSCDIV_DIV1_SHIFT (0)
135 #define SCG_SOSCDIV_DIV1_MASK ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT)
137 /* SCG RTC OSC Control Status Register */
138 #define SCG_ROSC_CSR_ROSCVLD_SHIFT (24)
139 #define SCG_ROSC_CSR_ROSCVLD_MASK ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT)
141 #define SCG_SPLL_CSR_SPLLVLD_SHIFT (24)
142 #define SCG_SPLL_CSR_SPLLVLD_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT)
143 #define SCG_SPLL_CSR_SPLLEN_SHIFT (0)
144 #define SCG_SPLL_CSR_SPLLEN_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT)
145 #define SCG_APLL_CSR_APLLEN_SHIFT (0)
146 #define SCG_APLL_CSR_APLLEN_MASK (0x1UL)
147 #define SCG_APLL_CSR_APLLVLD_MASK (0x01000000)
149 #define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000)
152 #define SCG_PLL_PFD3_GATE_MASK (0x80000000)
153 #define SCG_PLL_PFD2_GATE_MASK (0x00800000)
154 #define SCG_PLL_PFD1_GATE_MASK (0x00008000)
155 #define SCG_PLL_PFD0_GATE_MASK (0x00000080)
156 #define SCG_PLL_PFD3_VALID_MASK (0x40000000)
157 #define SCG_PLL_PFD2_VALID_MASK (0x00400000)
158 #define SCG_PLL_PFD1_VALID_MASK (0x00004000)
159 #define SCG_PLL_PFD0_VALID_MASK (0x00000040)
161 #define SCG_PLL_PFD0_FRAC_SHIFT (0)
162 #define SCG_PLL_PFD0_FRAC_MASK ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT)
163 #define SCG_PLL_PFD1_FRAC_SHIFT (8)
164 #define SCG_PLL_PFD1_FRAC_MASK ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT)
165 #define SCG_PLL_PFD2_FRAC_SHIFT (16)
166 #define SCG_PLL_PFD2_FRAC_MASK ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT)
167 #define SCG_PLL_PFD3_FRAC_SHIFT (24)
168 #define SCG_PLL_PFD3_FRAC_MASK ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT)
170 #define SCG_PLL_CFG_POSTDIV2_SHIFT (28)
171 #define SCG_PLL_CFG_POSTDIV2_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT)
172 #define SCG_PLL_CFG_POSTDIV1_SHIFT (24)
173 #define SCG_PLL_CFG_POSTDIV1_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT)
174 #define SCG_PLL_CFG_MULT_SHIFT (16)
175 #define SCG1_SPLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
176 #define SCG_APLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
177 #define SCG_PLL_CFG_PFDSEL_SHIFT (14)
178 #define SCG_PLL_CFG_PFDSEL_MASK ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT)
179 #define SCG_PLL_CFG_PREDIV_SHIFT (8)
180 #define SCG_PLL_CFG_PREDIV_MASK ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT)
181 #define SCG_PLL_CFG_BYPASS_SHIFT (2)
182 /* 0: SPLL, 1: bypass */
183 #define SCG_PLL_CFG_BYPASS_MASK ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT)
184 #define SCG_PLL_CFG_PLLSEL_SHIFT (1)
186 #define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT)
187 #define SCG_PLL_CFG_CLKSRC_SHIFT (0)
188 /* 0: Sys-OSC, 1: FIRC */
189 #define SCG_PLL_CFG_CLKSRC_MASK ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT)
190 #define SCG0_SPLL_CFG_MULT_SHIFT (17)
191 /* 0: Multiplier = 20, 1: Multiplier = 22 */
192 #define SCG0_SPLL_CFG_MULT_MASK ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT)
194 #define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6)
195 #define PLL_USB_PWR_MASK (0x01 << 12)
196 #define PLL_USB_ENABLE_MASK (0x01 << 13)
197 #define PLL_USB_BYPASS_MASK (0x01 << 16)
198 #define PLL_USB_REG_ENABLE_MASK (0x01 << 21)
199 #define PLL_USB_DIV_SEL_MASK (0x07 << 22)
200 #define PLL_USB_LOCK_MASK (0x01 << 31)
246 /* PLL supported by i.mx7ulp */
248 PLL_M4_SPLL, /* M4 SPLL */
249 PLL_M4_APLL, /* M4 APLL*/
250 PLL_A7_SPLL, /* A7 SPLL */
251 PLL_A7_APLL, /* A7 APLL */
252 PLL_USB, /* USB PLL*/
253 PLL_MIPI, /* MIPI PLL */
256 typedef struct scg_regs {
257 u32 verid; /* VERSION_ID */
258 u32 param; /* PARAMETER */
261 u32 csr; /* Clock Status Register */
262 u32 rccr; /* Run Clock Control Register */
263 u32 vccr; /* VLPR Clock Control Register */
264 u32 hccr; /* HSRUN Clock Control Register */
265 u32 clkoutcnfg; /* SCG CLKOUT Configuration Register */
267 u32 ddrccr; /* SCG DDR Clock Control Register */
269 u32 nicccr; /* NIC Clock Control Register */
270 u32 niccsr; /* NIC Clock Status Register */
273 u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */
274 u32 soscdiv; /* System OSC Divide Register */
275 u32 sosccfg; /* System Oscillator Configuration Register */
276 u32 sosctest; /* System Oscillator Test Register */
279 u32 sirccsr; /* Slow IRC Control Status Register, offset 0x200 */
280 u32 sircdiv; /* Slow IRC Divide Register */
281 u32 sirccfg; /* Slow IRC Configuration Register */
282 u32 sirctrim; /* Slow IRC Trim Register */
283 u32 loptrim; /* Low Power Oscillator Trim Register */
284 u32 sirctest; /* Slow IRC Test Register */
287 u32 firccsr; /* Fast IRC Control Status Register, offset 0x300 */
290 u32 firctcfg; /* Fast IRC Trim Configuration Register */
291 u32 firctriml; /* Fast IRC Trim Low Register */
293 u32 fircstat; /* Fast IRC Status Register */
294 u32 firctest; /* Fast IRC Test Register */
297 u32 rtccsr; /* RTC OSC Control Status Register, offset 0x400 */
300 u32 apllcsr; /* Auxiliary PLL Control Status Register, offset 0x500 */
301 u32 aplldiv; /* Auxiliary PLL Divider Register */
302 u32 apllcfg; /* Auxiliary PLL Configuration Register */
303 u32 apllpfd; /* Auxiliary PLL PFD Register */
304 u32 apllnum; /* Auxiliary PLL Numerator Register */
305 u32 aplldenom; /* Auxiliary PLL Denominator Register */
306 u32 apllss; /* Auxiliary PLL Spread Spectrum Register */
308 u32 apllock_cnfg; /* Auxiliary PLL LOCK Configuration Register */
311 u32 spllcsr; /* System PLL Control Status Register, offset 0x600 */
312 u32 splldiv; /* System PLL Divide Register */
313 u32 spllcfg; /* System PLL Configuration Register */
314 u32 spllpfd; /* System PLL Test Register */
315 u32 spllnum; /* System PLL Numerator Register */
316 u32 splldenom; /* System PLL Denominator Register */
317 u32 spllss; /* System PLL Spread Spectrum Register */
319 u32 spllock_cnfg; /* System PLL LOCK Configuration Register */
322 u32 upllcsr; /* USB PLL Control Status Register, offset 0x700 */
323 u32 uplldiv; /* USB PLL Divide Register */
324 u32 upllcfg; /* USB PLL Configuration Register */
327 u32 scg_clk_get_rate(enum scg_clk clk);
328 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
329 int scg_enable_usb_pll(bool usb_control);
330 u32 decode_pll(enum pll_clocks pll);
332 void scg_a7_rccr_init(void);
333 void scg_a7_spll_init(void);
334 void scg_a7_ddrclk_init(void);
335 void scg_a7_apll_init(void);
336 void scg_a7_firc_init(void);
337 void scg_a7_nicclk_init(void);
338 void scg_a7_sys_clk_sel(enum scg_sys_src clk);
339 void scg_a7_info(void);
340 void scg_a7_soscdiv_init(void);