1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __ASM_ARCH_MX8M_DDR_H
7 #define __ASM_ARCH_MX8M_DDR_H
9 #define DDRC_DDR_SS_GPR0 0x3d000000
10 #define DDRC_IPS_BASE_ADDR_0 0x3f400000
11 #define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
12 #define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
64 struct imx8m_ddrc_regs {
268 /* umctl2_regs_dch1 */
313 /* umctl2_regs_freq1 */
314 struct ddrc_freq freq1;
316 /* umctl2_regs_addrmap_alt */
330 /* umctl2_regs_freq2 */
331 struct ddrc_freq freq2;
333 /* umctl2_regs_freq3 */
334 struct ddrc_freq freq3;
337 struct imx8m_ddrphy_regs {
351 TRAIN_STREAM_START = 0x8,