4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_MX8M_REGS_H__
8 #define __ASM_ARCH_MX8M_REGS_H__
10 #include <asm/mach-imx/regs-lcdif.h>
12 #define ROM_VERSION_A0 0x800
13 #define ROM_VERSION_B0 0x83C
15 #define M4_BOOTROM_BASE_ADDR 0x007E0000
17 #define SAI1_BASE_ADDR 0x30010000
18 #define SAI6_BASE_ADDR 0x30030000
19 #define SAI5_BASE_ADDR 0x30040000
20 #define SAI4_BASE_ADDR 0x30050000
21 #define SPBA2_BASE_ADDR 0x300F0000
22 #define AIPS1_BASE_ADDR 0x301F0000
23 #define GPIO1_BASE_ADDR 0X30200000
24 #define GPIO2_BASE_ADDR 0x30210000
25 #define GPIO3_BASE_ADDR 0x30220000
26 #define GPIO4_BASE_ADDR 0x30230000
27 #define GPIO5_BASE_ADDR 0x30240000
28 #define ANA_TSENSOR_BASE_ADDR 0x30260000
29 #define ANA_OSC_BASE_ADDR 0x30270000
30 #define WDOG1_BASE_ADDR 0x30280000
31 #define WDOG2_BASE_ADDR 0x30290000
32 #define WDOG3_BASE_ADDR 0x302A0000
33 #define SDMA2_BASE_ADDR 0x302C0000
34 #define GPT1_BASE_ADDR 0x302D0000
35 #define GPT2_BASE_ADDR 0x302E0000
36 #define GPT3_BASE_ADDR 0x302F0000
37 #define ROMCP_BASE_ADDR 0x30310000
38 #define LCDIF_BASE_ADDR 0x30320000
39 #define IOMUXC_BASE_ADDR 0x30330000
40 #define IOMUXC_GPR_BASE_ADDR 0x30340000
41 #define OCOTP_BASE_ADDR 0x30350000
42 #define ANATOP_BASE_ADDR 0x30360000
43 #define SNVS_HP_BASE_ADDR 0x30370000
44 #define CCM_BASE_ADDR 0x30380000
45 #define SRC_BASE_ADDR 0x30390000
46 #define GPC_BASE_ADDR 0x303A0000
47 #define SEMAPHORE1_BASE_ADDR 0x303B0000
48 #define SEMAPHORE2_BASE_ADDR 0x303C0000
49 #define RDC_BASE_ADDR 0x303D0000
50 #define CSU_BASE_ADDR 0x303E0000
52 #define AIPS2_BASE_ADDR 0x305F0000
53 #define PWM1_BASE_ADDR 0x30660000
54 #define PWM2_BASE_ADDR 0x30670000
55 #define PWM3_BASE_ADDR 0x30680000
56 #define PWM4_BASE_ADDR 0x30690000
57 #define SYSCNT_RD_BASE_ADDR 0x306A0000
58 #define SYSCNT_CMP_BASE_ADDR 0x306B0000
59 #define SYSCNT_CTRL_BASE_ADDR 0x306C0000
60 #define GPT6_BASE_ADDR 0x306E0000
61 #define GPT5_BASE_ADDR 0x306F0000
62 #define GPT4_BASE_ADDR 0x30700000
63 #define PERFMON1_BASE_ADDR 0x307C0000
64 #define PERFMON2_BASE_ADDR 0x307D0000
65 #define QOSC_BASE_ADDR 0x307F0000
67 #define SPDIF1_BASE_ADDR 0x30810000
68 #define ECSPI1_BASE_ADDR 0x30820000
69 #define ECSPI2_BASE_ADDR 0x30830000
70 #define ECSPI3_BASE_ADDR 0x30840000
71 #define UART1_BASE_ADDR 0x30860000
72 #define UART3_BASE_ADDR 0x30880000
73 #define UART2_BASE_ADDR 0x30890000
74 #define SPDIF2_BASE_ADDR 0x308A0000
75 #define SAI2_BASE_ADDR 0x308B0000
76 #define SAI3_BASE_ADDR 0x308C0000
77 #define SPBA1_BASE_ADDR 0x308F0000
78 #define CAAM_BASE_ADDR 0x30900000
79 #define AIPS3_BASE_ADDR 0x309F0000
80 #define MIPI_PHY_BASE_ADDR 0x30A00000
81 #define MIPI_DSI_BASE_ADDR 0x30A10000
82 #define I2C1_BASE_ADDR 0x30A20000
83 #define I2C2_BASE_ADDR 0x30A30000
84 #define I2C3_BASE_ADDR 0x30A40000
85 #define I2C4_BASE_ADDR 0x30A50000
86 #define UART4_BASE_ADDR 0x30A60000
87 #define MIPI_CSI_BASE_ADDR 0x30A70000
88 #define MIPI_CSI_PHY1_BASE_ADDR 0x30A80000
89 #define CSI1_BASE_ADDR 0x30A90000
90 #define MU_A_BASE_ADDR 0x30AA0000
91 #define MU_B_BASE_ADDR 0x30AB0000
92 #define SEMAPHOR_HS_BASE_ADDR 0x30AC0000
93 #define USDHC1_BASE_ADDR 0x30B40000
94 #define USDHC2_BASE_ADDR 0x30B50000
95 #define MIPI_CS2_BASE_ADDR 0x30B60000
96 #define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000
97 #define CSI2_BASE_ADDR 0x30B80000
98 #define QSPI0_BASE_ADDR 0x30BB0000
99 #define QSPI0_AMBA_BASE 0x08000000
100 #define SDMA1_BASE_ADDR 0x30BD0000
101 #define ENET1_BASE_ADDR 0x30BE0000
103 #define HDMI_CTRL_BASE_ADDR 0x32C00000
104 #define AIPS4_BASE_ADDR 0x32DF0000
105 #define DC1_BASE_ADDR 0x32E00000
106 #define DC2_BASE_ADDR 0x32E10000
107 #define DC3_BASE_ADDR 0x32E20000
108 #define HDMI_SEC_BASE_ADDR 0x32E40000
109 #define TZASC_BASE_ADDR 0x32F80000
110 #define MTR_BASE_ADDR 0x32FB0000
111 #define PLATFORM_CTRL_BASE_ADDR 0x32FE0000
113 #define MXS_APBH_BASE 0x33000000
114 #define MXS_GPMI_BASE 0x33002000
115 #define MXS_BCH_BASE 0x33004000
117 #define USB1_BASE_ADDR 0x38100000
118 #define USB2_BASE_ADDR 0x38200000
119 #define USB1_PHY_BASE_ADDR 0x381F0000
120 #define USB2_PHY_BASE_ADDR 0x382F0000
122 #define MXS_LCDIF_BASE LCDIF_BASE_ADDR
124 #define SRC_IPS_BASE_ADDR 0x30390000
125 #define SRC_DDRC_RCR_ADDR 0x30391000
126 #define SRC_DDRC2_RCR_ADDR 0x30391004
128 #define DDRC_DDR_SS_GPR0 0x3d000000
129 #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
130 #define DDR_CSD1_BASE_ADDR 0x40000000
132 #if !defined(__ASSEMBLY__)
133 #include <asm/types.h>
134 #include <linux/bitops.h>
137 #define GPR_TZASC_EN BIT(0)
138 #define GPR_TZASC_EN_LOCK BIT(16)
140 #define SRC_SCR_M4_ENABLE_OFFSET 3
141 #define SRC_SCR_M4_ENABLE_MASK BIT(3)
142 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
143 #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
144 #define SRC_DDR1_ENABLE_MASK 0x8F000000UL
145 #define SRC_DDR2_ENABLE_MASK 0x8F000000UL
146 #define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
147 #define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2)
148 #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
149 #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
151 struct iomuxc_gpr_base_regs {
187 struct fuse_bank0_regs {
196 struct fuse_bank1_regs {
237 u32 pllout_monitor_cfg;
238 u32 frac_pllout_div_cfg;
239 u32 sscg_pllout_div_cfg;
242 struct fuse_bank9_regs {
249 /* System Reset Controller (SRC) */
298 u32 mmdc_cpu_mapping;
350 u32 pgc_cpu_0_1_mapping;
358 u32 pgc_cpu_2_3_mapping;
367 u32 cpu_pgc_up_status1;
368 u32 mix_pgc_up_status0;
369 u32 mix_pgc_up_status1;
370 u32 mix_pgc_up_status2;
371 u32 m4_mix_pgc_up_status0;
372 u32 m4_mix_pgc_up_status1;
373 u32 m4_mix_pgc_up_status2;
374 u32 pu_pgc_up_status0;
375 u32 pu_pgc_up_status1;
376 u32 pu_pgc_up_status2;
377 u32 m4_pu_pgc_up_status0;
378 u32 m4_pu_pgc_up_status1;
379 u32 m4_pu_pgc_up_status2;
383 u32 cpu_pgc_dn_status1;
384 u32 mix_pgc_dn_status0;
385 u32 mix_pgc_dn_status1;
386 u32 mix_pgc_dn_status2;
387 u32 m4_mix_pgc_dn_status0;
388 u32 m4_mix_pgc_dn_status1;
389 u32 m4_mix_pgc_dn_status2;
390 u32 pu_pgc_dn_status0;
391 u32 pu_pgc_dn_status1;
392 u32 pu_pgc_dn_status2;
393 u32 m4_pu_pgc_dn_status0;
394 u32 m4_pu_pgc_dn_status1;
395 u32 m4_pu_pgc_dn_status2;
410 u32 pgc_ack_sel_m4_pu;
439 #define WDOG_WDT_MASK BIT(3)
440 #define WDOG_WDZST_MASK BIT(0)
442 u16 wcr; /* Control */
443 u16 wsr; /* Service */
444 u16 wrsr; /* Reset Status */
445 u16 wicr; /* Interrupt Control */
446 u16 wmcr; /* Miscellaneous Control */
449 struct bootrom_sw_info {
451 u8 boot_dev_instance;
461 #define ROM_SW_INFO_ADDR_B0 0x00000968
462 #define ROM_SW_INFO_ADDR_A0 0x000009e8
464 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
465 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
466 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0