2 * Freescale i.MX28 APBH DMA
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/list.h>
30 #include <linux/compiler.h>
32 #ifndef CONFIG_ARCH_DMA_PIO_WORDS
33 #define DMA_PIO_WORDS 15
35 #define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
38 #define MXS_DMA_ALIGNMENT 32
43 #if defined(CONFIG_MX23)
45 MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
46 MXS_DMA_CHANNEL_AHB_APBH_SSP0,
47 MXS_DMA_CHANNEL_AHB_APBH_SSP1,
48 MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
49 MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
50 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
51 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
52 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
55 #elif defined(CONFIG_MX28)
57 MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
58 MXS_DMA_CHANNEL_AHB_APBH_SSP1,
59 MXS_DMA_CHANNEL_AHB_APBH_SSP2,
60 MXS_DMA_CHANNEL_AHB_APBH_SSP3,
61 MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
62 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
63 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
64 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
65 MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
66 MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
67 MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
68 MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
69 MXS_DMA_CHANNEL_AHB_APBH_HSADC,
70 MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
71 MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
72 MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
78 * MXS DMA hardware command.
80 * This structure describes the in-memory layout of an entire DMA command,
81 * including space for the maximum number of PIO accesses. See the appropriate
82 * reference manual for a detailed description of what these fields mean to the
85 #define MXS_DMA_DESC_COMMAND_MASK 0x3
86 #define MXS_DMA_DESC_COMMAND_OFFSET 0
87 #define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
88 #define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
89 #define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
90 #define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
91 #define MXS_DMA_DESC_CHAIN (1 << 2)
92 #define MXS_DMA_DESC_IRQ (1 << 3)
93 #define MXS_DMA_DESC_NAND_LOCK (1 << 4)
94 #define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
95 #define MXS_DMA_DESC_DEC_SEM (1 << 6)
96 #define MXS_DMA_DESC_WAIT4END (1 << 7)
97 #define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
98 #define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
99 #define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
100 #define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
101 #define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
102 #define MXS_DMA_DESC_BYTES_OFFSET 16
109 unsigned long alternate;
111 unsigned long pio_words[DMA_PIO_WORDS];
115 * MXS DMA command descriptor.
117 * This structure incorporates an MXS DMA hardware command structure, along
120 #define MXS_DMA_DESC_FIRST (1 << 0)
121 #define MXS_DMA_DESC_LAST (1 << 1)
122 #define MXS_DMA_DESC_READY (1 << 31)
124 struct mxs_dma_desc {
125 struct mxs_dma_cmd cmd;
129 struct list_head node;
130 } __aligned(MXS_DMA_ALIGNMENT);
135 * This structure represents a single DMA channel. The MXS platform code
136 * maintains an array of these structures to represent every DMA channel in the
137 * system (see mxs_dma_channels).
139 #define MXS_DMA_FLAGS_IDLE 0
140 #define MXS_DMA_FLAGS_BUSY (1 << 0)
141 #define MXS_DMA_FLAGS_FREE 0
142 #define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
143 #define MXS_DMA_FLAGS_VALID (1 << 31)
145 struct mxs_dma_chan {
148 struct mxs_dma_device *dma;
150 unsigned int active_num;
151 unsigned int pending_num;
152 struct list_head active;
153 struct list_head done;
156 struct mxs_dma_desc *mxs_dma_desc_alloc(void);
157 void mxs_dma_desc_free(struct mxs_dma_desc *);
158 int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
160 int mxs_dma_go(int chan);
161 void mxs_dma_init(void);
162 int mxs_dma_init_channel(int chan);
163 int mxs_dma_release(int chan);
165 #endif /* __DMA_H__ */