2 * Freescale i.MX28 Peripheral Base Addresses
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2008 Embedded Alley Solutions Inc.
10 * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #ifndef __MX28_REGS_BASE_H__
29 #define __MX28_REGS_BASE_H__
32 * Register base address
34 #define MXS_ICOL_BASE 0x80000000
35 #define MXS_HSADC_BASE 0x80002000
36 #define MXS_APBH_BASE 0x80004000
37 #define MXS_PERFMON_BASE 0x80006000
38 #define MXS_BCH_BASE 0x8000A000
39 #define MXS_GPMI_BASE 0x8000C000
40 #define MXS_SSP0_BASE 0x80010000
41 #define MXS_SSP1_BASE 0x80012000
42 #define MXS_SSP2_BASE 0x80014000
43 #define MXS_SSP3_BASE 0x80016000
44 #define MXS_PINCTRL_BASE 0x80018000
45 #define MXS_DIGCTL_BASE 0x8001C000
46 #define MXS_ETM_BASE 0x80022000
47 #define MXS_APBX_BASE 0x80024000
48 #define MXS_DCP_BASE 0x80028000
49 #define MXS_PXP_BASE 0x8002A000
50 #define MXS_OCOTP_BASE 0x8002C000
51 #define MXS_AXI_AHB0_BASE 0x8002E000
52 #define MXS_LCDIF_BASE 0x80030000
53 #define MXS_CAN0_BASE 0x80032000
54 #define MXS_CAN1_BASE 0x80034000
55 #define MXS_SIMDBG_BASE 0x8003C000
56 #define MXS_SIMGPMISEL_BASE 0x8003C200
57 #define MXS_SIMSSPSEL_BASE 0x8003C300
58 #define MXS_SIMMEMSEL_BASE 0x8003C400
59 #define MXS_GPIOMON_BASE 0x8003C500
60 #define MXS_SIMENET_BASE 0x8003C700
61 #define MXS_ARMJTAG_BASE 0x8003C800
62 #define MXS_CLKCTRL_BASE 0x80040000
63 #define MXS_SAIF0_BASE 0x80042000
64 #define MXS_POWER_BASE 0x80044000
65 #define MXS_SAIF1_BASE 0x80046000
66 #define MXS_LRADC_BASE 0x80050000
67 #define MXS_SPDIF_BASE 0x80054000
68 #define MXS_RTC_BASE 0x80056000
69 #define MXS_I2C0_BASE 0x80058000
70 #define MXS_I2C1_BASE 0x8005A000
71 #define MXS_PWM_BASE 0x80064000
72 #define MXS_TIMROT_BASE 0x80068000
73 #define MXS_UARTAPP0_BASE 0x8006A000
74 #define MXS_UARTAPP1_BASE 0x8006C000
75 #define MXS_UARTAPP2_BASE 0x8006E000
76 #define MXS_UARTAPP3_BASE 0x80070000
77 #define MXS_UARTAPP4_BASE 0x80072000
78 #define MXS_UARTDBG_BASE 0x80074000
79 #define MXS_USBPHY0_BASE 0x8007C000
80 #define MXS_USBPHY1_BASE 0x8007E000
81 #define MXS_USBCTRL0_BASE 0x80080000
82 #define MXS_USBCTRL1_BASE 0x80090000
83 #define MXS_DFLPT_BASE 0x800C0000
84 #define MXS_DRAM_BASE 0x800E0000
85 #define MXS_ENET0_BASE 0x800F0000
86 #define MXS_ENET1_BASE 0x800F4000
88 #endif /* __MX28_REGS_BASE_H__ */