2 * Freescale i.MX28 I2C Register Definitions
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __MX28_REGS_I2C_H__
11 #define __MX28_REGS_I2C_H__
13 #include <asm/mach-imx/regs-common.h>
17 mxs_reg_32(hw_i2c_ctrl0)
18 mxs_reg_32(hw_i2c_timing0)
19 mxs_reg_32(hw_i2c_timing1)
20 mxs_reg_32(hw_i2c_timing2)
21 mxs_reg_32(hw_i2c_ctrl1)
22 mxs_reg_32(hw_i2c_stat)
23 mxs_reg_32(hw_i2c_queuectrl)
24 mxs_reg_32(hw_i2c_queuestat)
25 mxs_reg_32(hw_i2c_queuecmd)
26 mxs_reg_32(hw_i2c_queuedata)
27 mxs_reg_32(hw_i2c_data)
28 mxs_reg_32(hw_i2c_debug0)
29 mxs_reg_32(hw_i2c_debug1)
30 mxs_reg_32(hw_i2c_version)
34 #define I2C_CTRL_SFTRST (1 << 31)
35 #define I2C_CTRL_CLKGATE (1 << 30)
36 #define I2C_CTRL_RUN (1 << 29)
37 #define I2C_CTRL_PREACK (1 << 27)
38 #define I2C_CTRL_ACKNOWLEDGE (1 << 26)
39 #define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25)
40 #define I2C_CTRL_MULTI_MASTER (1 << 23)
41 #define I2C_CTRL_CLOCK_HELD (1 << 22)
42 #define I2C_CTRL_RETAIN_CLOCK (1 << 21)
43 #define I2C_CTRL_POST_SEND_STOP (1 << 20)
44 #define I2C_CTRL_PRE_SEND_START (1 << 19)
45 #define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18)
46 #define I2C_CTRL_MASTER_MODE (1 << 17)
47 #define I2C_CTRL_DIRECTION (1 << 16)
48 #define I2C_CTRL_XFER_COUNT_MASK 0xffff
49 #define I2C_CTRL_XFER_COUNT_OFFSET 0
51 #define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16)
52 #define I2C_TIMING0_HIGH_COUNT_OFFSET 16
53 #define I2C_TIMING0_RCV_COUNT_MASK 0x3ff
54 #define I2C_TIMING0_RCV_COUNT_OFFSET 0
56 #define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16)
57 #define I2C_TIMING1_LOW_COUNT_OFFSET 16
58 #define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff
59 #define I2C_TIMING1_XMIT_COUNT_OFFSET 0
61 #define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16)
62 #define I2C_TIMING2_BUS_FREE_OFFSET 16
63 #define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff
64 #define I2C_TIMING2_LEADIN_COUNT_OFFSET 0
66 #define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30)
67 #define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29)
68 #define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28)
69 #define I2C_CTRL1_ACK_MODE (1 << 27)
70 #define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26)
71 #define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25)
72 #define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24)
73 #define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16)
74 #define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16
75 #define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15)
76 #define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14)
77 #define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13)
78 #define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12)
79 #define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11)
80 #define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10)
81 #define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9)
82 #define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8)
83 #define I2C_CTRL1_BUS_FREE_IRQ (1 << 7)
84 #define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6)
85 #define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5)
86 #define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4)
87 #define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3)
88 #define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2)
89 #define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1)
90 #define I2C_CTRL1_SLAVE_IRQ (1 << 0)
92 #define I2C_STAT_MASTER_PRESENT (1 << 31)
93 #define I2C_STAT_SLAVE_PRESENT (1 << 30)
94 #define I2C_STAT_ANY_ENABLED_IRQ (1 << 29)
95 #define I2C_STAT_GOT_A_NAK (1 << 28)
96 #define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16)
97 #define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16
98 #define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15)
99 #define I2C_STAT_SLAVE_FOUND (1 << 14)
100 #define I2C_STAT_SLAVE_SEARCHING (1 << 13)
101 #define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12)
102 #define I2C_STAT_BUS_BUSY (1 << 11)
103 #define I2C_STAT_CLK_GEN_BUSY (1 << 10)
104 #define I2C_STAT_DATA_ENGINE_BUSY (1 << 9)
105 #define I2C_STAT_SLAVE_BUSY (1 << 8)
106 #define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7)
107 #define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6)
108 #define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5)
109 #define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4)
110 #define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3)
111 #define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2)
112 #define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1)
113 #define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0)
115 #define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16)
116 #define I2C_QUEUECTRL_RD_THRESH_OFFSET 16
117 #define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8)
118 #define I2C_QUEUECTRL_WR_THRESH_OFFSET 8
119 #define I2C_QUEUECTRL_QUEUE_RUN (1 << 5)
120 #define I2C_QUEUECTRL_RD_CLEAR (1 << 4)
121 #define I2C_QUEUECTRL_WR_CLEAR (1 << 3)
122 #define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2)
123 #define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1)
124 #define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0)
126 #define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14)
127 #define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13)
128 #define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8)
129 #define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8
130 #define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6)
131 #define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5)
132 #define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f
133 #define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0
135 #define I2C_QUEUECMD_PREACK (1 << 27)
136 #define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26)
137 #define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25)
138 #define I2C_QUEUECMD_MULTI_MASTER (1 << 23)
139 #define I2C_QUEUECMD_CLOCK_HELD (1 << 22)
140 #define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21)
141 #define I2C_QUEUECMD_POST_SEND_STOP (1 << 20)
142 #define I2C_QUEUECMD_PRE_SEND_START (1 << 19)
143 #define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18)
144 #define I2C_QUEUECMD_MASTER_MODE (1 << 17)
145 #define I2C_QUEUECMD_DIRECTION (1 << 16)
146 #define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff
147 #define I2C_QUEUECMD_XFER_COUNT_OFFSET 0
149 #define I2C_QUEUEDATA_DATA_MASK 0xffffffff
150 #define I2C_QUEUEDATA_DATA_OFFSET 0
152 #define I2C_DATA_DATA_MASK 0xffffffff
153 #define I2C_DATA_DATA_OFFSET 0
155 #define I2C_DEBUG0_DMAREQ (1 << 31)
156 #define I2C_DEBUG0_DMAENDCMD (1 << 30)
157 #define I2C_DEBUG0_DMAKICK (1 << 29)
158 #define I2C_DEBUG0_DMATERMINATE (1 << 28)
159 #define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26)
160 #define I2C_DEBUG0_STATE_VALUE_OFFSET 26
161 #define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16)
162 #define I2C_DEBUG0_DMA_STATE_OFFSET 16
163 #define I2C_DEBUG0_START_TOGGLE (1 << 15)
164 #define I2C_DEBUG0_STOP_TOGGLE (1 << 14)
165 #define I2C_DEBUG0_GRAB_TOGGLE (1 << 13)
166 #define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12)
167 #define I2C_DEBUG0_STATE_LATCH (1 << 11)
168 #define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10)
169 #define I2C_DEBUG0_STATE_STATE_MASK 0x3ff
170 #define I2C_DEBUG0_STATE_STATE_OFFSET 0
172 #define I2C_DEBUG1_I2C_CLK_IN (1 << 31)
173 #define I2C_DEBUG1_I2C_DATA_IN (1 << 30)
174 #define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24)
175 #define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24
176 #define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16)
177 #define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16
178 #define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9)
179 #define I2C_DEBUG1_LST_MODE_OFFSET 9
180 #define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8)
181 #define I2C_DEBUG1_FORCE_CLK_ON (1 << 4)
182 #define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3)
183 #define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2)
184 #define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1)
185 #define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0)
187 #define I2C_VERSION_MAJOR_MASK (0xff << 24)
188 #define I2C_VERSION_MAJOR_OFFSET 24
189 #define I2C_VERSION_MINOR_MASK (0xff << 16)
190 #define I2C_VERSION_MINOR_OFFSET 16
191 #define I2C_VERSION_STEP_MASK 0xffff
192 #define I2C_VERSION_STEP_OFFSET 0
194 #endif /* __MX28_REGS_I2C_H__ */