2 * am35x_def.h - TI's AM35x specific definitions.
4 * Based on arch/arm/include/asm/arch-omap3/cpu.h
6 * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
8 * Copyright (c) 2010 Texas Instruments Incorporated
10 * SPDX-License-Identifier: GPL-2.0+
16 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
17 #include <asm/types.h>
18 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
20 #ifndef __KERNEL_STRICT_NAMES
23 /* LVL_INTR_CLEAR bits */
24 #define USBOTGSS_INT_CLR (1 << 4)
26 /* IP_SW_RESET bits */
27 #define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */
28 #define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */
31 #define CONF2_PHY_GPIOMODE (1 << 23)
32 #define CONF2_OTGMODE (3 << 14)
33 #define CONF2_NO_OVERRIDE (0 << 14)
34 #define CONF2_FORCE_HOST (1 << 14)
35 #define CONF2_FORCE_DEVICE (2 << 14)
36 #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
37 #define CONF2_SESENDEN (1 << 13)
38 #define CONF2_VBDTCTEN (1 << 12)
39 #define CONF2_REFFREQ_24MHZ (2 << 8)
40 #define CONF2_REFFREQ_26MHZ (7 << 8)
41 #define CONF2_REFFREQ_13MHZ (6 << 8)
42 #define CONF2_REFFREQ (0xf << 8)
43 #define CONF2_PHYCLKGD (1 << 7)
44 #define CONF2_VBUSSENSE (1 << 6)
45 #define CONF2_PHY_PLLON (1 << 5)
46 #define CONF2_RESET (1 << 4)
47 #define CONF2_PHYPWRDN (1 << 3)
48 #define CONF2_OTGPWRDN (1 << 2)
49 #define CONF2_DATPOL (1 << 1)
51 /* General register mappings of system control module */
52 #define AM35X_SCM_GEN_BASE 0x48002270
53 struct am35x_scm_general {
54 u32 res1[0xC4]; /* 0x000 - 0x30C */
55 u32 devconf2; /* 0x310 */
56 u32 devconf3; /* 0x314 */
57 u32 res2[0x2]; /* 0x318 - 0x31C */
58 u32 cba_priority; /* 0x320 */
59 u32 lvl_intr_clr; /* 0x324 */
60 u32 ip_sw_reset; /* 0x328 */
61 u32 ipss_clk_ctrl; /* 0x32C */
63 #define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE)
65 #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
67 #endif /*__ASSEMBLY__ */
68 #endif /* __KERNEL_STRICT_NAMES */
70 #endif /* _AM35X_DEF_H_ */