2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
12 #include <asm/types.h>
13 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
15 /* Register offsets of common modules */
17 #ifndef __KERNEL_STRICT_NAMES
21 u16 gpmc_nadv_ale; /* 0xC0 */
22 u16 gpmc_noe; /* 0xC2 */
23 u16 gpmc_nwe; /* 0xC4 */
25 u32 status; /* 0x2F0 */
26 u32 gpstatus; /* 0x2F4 */
28 u32 rpubkey_0; /* 0x300 */
29 u32 rpubkey_1; /* 0x304 */
30 u32 rpubkey_2; /* 0x308 */
31 u32 rpubkey_3; /* 0x30C */
32 u32 rpubkey_4; /* 0x310 */
34 u32 randkey_0; /* 0x318 */
35 u32 randkey_1; /* 0x31C */
36 u32 randkey_2; /* 0x320 */
37 u32 randkey_3; /* 0x324 */
39 u32 ctrl_omap_stat; /* 0x44C */
41 #else /* __ASSEMBLY__ */
42 #define CONTROL_STATUS 0x2F0
43 #endif /* __ASSEMBLY__ */
44 #endif /* __KERNEL_STRICT_NAMES */
46 #ifndef __KERNEL_STRICT_NAMES
50 u32 idcode; /* 0x04 */
51 u32 prod_id; /* 0x08 */
52 u32 sku_id; /* 0x0c */
54 u32 die_id_0; /* 0x18 */
55 u32 die_id_1; /* 0x1C */
56 u32 die_id_2; /* 0x20 */
57 u32 die_id_3; /* 0x24 */
59 #endif /* __ASSEMBLY__ */
60 #endif /* __KERNEL_STRICT_NAMES */
63 #define DEVICE_MASK (0x7 << 8)
64 #define SYSBOOT_MASK 0x1F
65 #define TST_DEVICE 0x0
66 #define EMU_DEVICE 0x1
71 #define SKUID_CLK_MASK 0xf
72 #define SKUID_CLK_600MHZ 0x0
73 #define SKUID_CLK_720MHZ 0x8
75 #define GPMC_BASE (OMAP34XX_GPMC_BASE)
76 #define GPMC_CONFIG_CS0 0x60
77 #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
79 #ifndef __KERNEL_STRICT_NAMES
81 #define GPMC_CONFIG1 0x00
82 #define GPMC_CONFIG2 0x04
83 #define GPMC_CONFIG3 0x08
84 #define GPMC_CONFIG4 0x0C
85 #define GPMC_CONFIG5 0x10
86 #define GPMC_CONFIG6 0x14
87 #define GPMC_CONFIG7 0x18
88 #endif /* __ASSEMBLY__ */
89 #endif /* __KERNEL_STRICT_NAMES */
92 #define FLASH_BASE 0x10000000 /* NOR flash, */
93 /* aligned to 256 Meg */
94 #define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
95 /* aligned to 64 Meg */
96 #define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
97 /* aligned to 256 Meg */
98 #define DEBUG_BASE 0x08000000 /* debug board */
99 #define NAND_BASE 0x30000000 /* NAND addr */
100 /* (actual size small port) */
101 #define ONENAND_MAP 0x20000000 /* OneNand addr */
102 /* (actual size small port) */
104 #ifndef __KERNEL_STRICT_NAMES
108 u32 sysconfig; /* 0x10 */
110 u32 rg_att0; /* 0x48 */
112 u32 class_arb0; /* 0xD0 */
114 #endif /* __ASSEMBLY__ */
115 #endif /* __KERNEL_STRICT_NAMES */
117 #define BURSTCOMPLETE_GROUP7 (0x1 << 31)
120 #ifndef __KERNEL_STRICT_NAMES
123 u32 mcfg; /* 0x80 || 0xB0 */
124 u32 mr; /* 0x84 || 0xB4 */
126 u32 emr2; /* 0x8C || 0xBC */
128 u32 rfr_ctrl; /* 0x84 || 0xD4 */
129 u32 manual; /* 0xA8 || 0xD8 */
134 u32 ctrla; /* 0x9C || 0xC4 */
135 u32 ctrlb; /* 0xA0 || 0xC8 */
140 u32 sysconfig; /* 0x10 */
141 u32 status; /* 0x14 */
143 u32 cs_cfg; /* 0x40 */
144 u32 sharing; /* 0x44 */
146 u32 dlla_ctrl; /* 0x60 */
147 u32 dlla_status; /* 0x64 */
148 u32 dllb_ctrl; /* 0x68 */
149 u32 dllb_status; /* 0x6C */
150 u32 power; /* 0x70 */
152 struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */
156 typedef struct emif4 {
157 unsigned int emif_mod_id_rev;
158 unsigned int sdram_sts;
159 unsigned int sdram_config;
161 unsigned int sdram_refresh_ctrl;
162 unsigned int sdram_refresh_ctrl_shdw;
163 unsigned int sdram_time1;
164 unsigned int sdram_time1_shdw;
165 unsigned int sdram_time2;
166 unsigned int sdram_time2_shdw;
167 unsigned int sdram_time3;
168 unsigned int sdram_time3_shdw;
169 unsigned char res2[8];
170 unsigned int sdram_pwr_mgmt;
171 unsigned int sdram_pwr_mgmt_shdw;
172 unsigned char res3[32];
173 unsigned int sdram_iodft_tlgc;
174 unsigned char res4[128];
175 unsigned int ddr_phyctrl1;
176 unsigned int ddr_phyctrl1_shdw;
177 unsigned int ddr_phyctrl2;
180 #endif /* __ASSEMBLY__ */
181 #endif /* __KERNEL_STRICT_NAMES */
183 #define DLLPHASE_90 (0x1 << 1)
184 #define LOADDLL (0x1 << 2)
185 #define ENADLL (0x1 << 3)
186 #define DLL_DELAY_MASK 0xFF00
187 #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
189 #define PAGEPOLICY_HIGH (0x1 << 0)
190 #define SRFRONRESET (0x1 << 7)
191 #define PWDNEN (0x1 << 2)
192 #define WAKEUPPROC (0x1 << 26)
194 #define DDR_SDRAM (0x1 << 0)
195 #define DEEPPD (0x1 << 3)
196 #define B32NOT16 (0x1 << 4)
197 #define BANKALLOCATION (0x2 << 6)
198 #define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
199 #define ADDRMUXLEGACY (0x1 << 19)
200 #define CASWIDTH_10BITS (0x5 << 20)
201 #define RASWIDTH_13BITS (0x2 << 24)
202 #define BURSTLENGTH4 (0x2 << 0)
203 #define CASL3 (0x3 << 4)
204 #define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
205 #define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
206 #define ARE_ARCV_1 (0x1 << 0)
207 #define ARCV (0x4e2 << 8) /* Autorefresh count */
208 #define OMAP34XX_SDRC_CS0 0x80000000
209 #define OMAP34XX_SDRC_CS1 0xA0000000
211 #define CMD_PRECHARGE 0x1
212 #define CMD_AUTOREFRESH 0x2
213 #define CMD_ENTR_PWRDOWN 0x3
214 #define CMD_EXIT_PWRDOWN 0x4
215 #define CMD_ENTR_SRFRSH 0x5
216 #define CMD_CKE_HIGH 0x6
217 #define CMD_CKE_LOW 0x7
218 #define SOFTRESET (0x1 << 1)
219 #define SMART_IDLE (0x2 << 3)
220 #define REF_ON_IDLE (0x1 << 6)
223 #ifndef __KERNEL_STRICT_NAMES
249 u32 irqstatus_l[0x4];
250 u32 irqenable_l[0x4];
261 struct dma4_chan chan[32];
264 #endif /*__ASSEMBLY__ */
265 #endif /* __KERNEL_STRICT_NAMES */
267 /* timer regs offsets (32 bit regs) */
269 #ifndef __KERNEL_STRICT_NAMES
272 u32 tidr; /* 0x00 r */
274 u32 tiocp_cfg; /* 0x10 rw */
275 u32 tistat; /* 0x14 r */
276 u32 tisr; /* 0x18 rw */
277 u32 tier; /* 0x1c rw */
278 u32 twer; /* 0x20 rw */
279 u32 tclr; /* 0x24 rw */
280 u32 tcrr; /* 0x28 rw */
281 u32 tldr; /* 0x2c rw */
282 u32 ttgr; /* 0x30 rw */
283 u32 twpc; /* 0x34 r*/
284 u32 tmar; /* 0x38 rw*/
285 u32 tcar1; /* 0x3c r */
286 u32 tcicr; /* 0x40 rw */
287 u32 tcar2; /* 0x44 r */
289 #endif /* __ASSEMBLY__ */
290 #endif /* __KERNEL_STRICT_NAMES */
292 /* enable sys_clk NO-prescale /1 */
293 #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
296 #ifndef __KERNEL_STRICT_NAMES
300 u32 wwps; /* 0x34 r */
302 u32 wspr; /* 0x48 rw */
304 #endif /* __ASSEMBLY__ */
305 #endif /* __KERNEL_STRICT_NAMES */
307 #define WD_UNLOCK1 0xAAAA
308 #define WD_UNLOCK2 0x5555
311 #define PRCM_BASE 0x48004000
313 #ifndef __KERNEL_STRICT_NAMES
316 u32 fclken_iva2; /* 0x00 */
317 u32 clken_pll_iva2; /* 0x04 */
319 u32 idlest_pll_iva2; /* 0x24 */
321 u32 clksel1_pll_iva2 ; /* 0x40 */
322 u32 clksel2_pll_iva2; /* 0x44 */
324 u32 clken_pll_mpu; /* 0x904 */
326 u32 idlest_pll_mpu; /* 0x924 */
328 u32 clksel1_pll_mpu; /* 0x940 */
329 u32 clksel2_pll_mpu; /* 0x944 */
331 u32 fclken1_core; /* 0xa00 */
332 u32 res_fclken2_core;
333 u32 fclken3_core; /* 0xa08 */
335 u32 iclken1_core; /* 0xa10 */
336 u32 iclken2_core; /* 0xa14 */
337 u32 iclken3_core; /* 0xa18 */
339 u32 clksel_core; /* 0xa40 */
341 u32 fclken_gfx; /* 0xb00 */
343 u32 iclken_gfx; /* 0xb10 */
345 u32 clksel_gfx; /* 0xb40 */
347 u32 fclken_wkup; /* 0xc00 */
349 u32 iclken_wkup; /* 0xc10 */
351 u32 idlest_wkup; /* 0xc20 */
353 u32 clksel_wkup; /* 0xc40 */
355 u32 clken_pll; /* 0xd00 */
356 u32 clken2_pll; /* 0xd04 */
358 u32 idlest_ckgen; /* 0xd20 */
359 u32 idlest2_ckgen; /* 0xd24 */
361 u32 clksel1_pll; /* 0xd40 */
362 u32 clksel2_pll; /* 0xd44 */
363 u32 clksel3_pll; /* 0xd48 */
364 u32 clksel4_pll; /* 0xd4c */
365 u32 clksel5_pll; /* 0xd50 */
367 u32 fclken_dss; /* 0xe00 */
369 u32 iclken_dss; /* 0xe10 */
371 u32 clksel_dss; /* 0xe40 */
373 u32 fclken_cam; /* 0xf00 */
375 u32 iclken_cam; /* 0xf10 */
377 u32 clksel_cam; /* 0xf40 */
379 u32 fclken_per; /* 0x1000 */
381 u32 iclken_per; /* 0x1010 */
383 u32 clksel_per; /* 0x1040 */
385 u32 clksel1_emu; /* 0x1140 */
387 u32 fclken_usbhost; /* 0x1400 */
389 u32 iclken_usbhost; /* 0x1410 */
391 #else /* __ASSEMBLY__ */
392 #define CM_CLKSEL_CORE 0x48004a40
393 #define CM_CLKSEL_GFX 0x48004b40
394 #define CM_CLKSEL_WKUP 0x48004c40
395 #define CM_CLKEN_PLL 0x48004d00
396 #define CM_CLKSEL1_PLL 0x48004d40
397 #define CM_CLKSEL1_EMU 0x48005140
398 #endif /* __ASSEMBLY__ */
399 #endif /* __KERNEL_STRICT_NAMES */
401 #define PRM_BASE 0x48306000
403 #ifndef __KERNEL_STRICT_NAMES
407 u32 clksel; /* 0xd40 */
409 u32 rstctrl; /* 0x1250 */
411 u32 clksrc_ctrl; /* 0x1270 */
413 #endif /* __ASSEMBLY__ */
414 #endif /* __KERNEL_STRICT_NAMES */
416 #define PRM_RSTCTRL 0x48307250
417 #define PRM_RSTCTRL_RESET 0x04
418 #define PRM_RSTST 0x48307258
419 #define PRM_RSTST_WARM_RESET_MASK 0x7D2
420 #define SYSCLKDIV_1 (0x1 << 6)
421 #define SYSCLKDIV_2 (0x1 << 7)
423 #define CLKSEL_GPT1 (0x1 << 0)
425 #define EN_GPT1 (0x1 << 0)
426 #define EN_32KSYNC (0x1 << 2)
428 #define ST_WDT2 (0x1 << 5)
430 #define ST_MPU_CLK (0x1 << 0)
432 #define ST_CORE_CLK (0x1 << 0)
434 #define ST_PERIPH_CLK (0x1 << 1)
436 #define ST_IVA2_CLK (0x1 << 0)
438 #define RESETDONE (0x1 << 0)
440 #define TCLR_ST (0x1 << 0)
441 #define TCLR_AR (0x1 << 1)
442 #define TCLR_PRE (0x1 << 5)
445 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
446 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
447 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
448 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
450 #ifndef __KERNEL_STRICT_NAMES
454 u32 req_info_permission_0; /* 0x48 */
456 u32 read_permission_0; /* 0x50 */
458 u32 wirte_permission_0; /* 0x58 */
460 u32 addr_match_1; /* 0x58 */
462 u32 req_info_permission_1; /* 0x68 */
464 u32 addr_match_2; /* 0x80 */
466 #endif /*__ASSEMBLY__ */
467 #endif /* __KERNEL_STRICT_NAMES */
469 /* Permission values for registers -Full fledged permissions to all */
470 #define UNLOCK_1 0xFFFFFFFF
471 #define UNLOCK_2 0x00000000
472 #define UNLOCK_3 0x0000FFFF
477 #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
478 #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
479 #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
482 #define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
484 /* OMAP3 GPIO registers */
485 #define OMAP_GPIO_REVISION 0x0000
486 #define OMAP_GPIO_SYSCONFIG 0x0010
487 #define OMAP_GPIO_SYSSTATUS 0x0014
488 #define OMAP_GPIO_IRQSTATUS1 0x0018
489 #define OMAP_GPIO_IRQSTATUS2 0x0028
490 #define OMAP_GPIO_IRQENABLE2 0x002c
491 #define OMAP_GPIO_IRQENABLE1 0x001c
492 #define OMAP_GPIO_WAKE_EN 0x0020
493 #define OMAP_GPIO_CTRL 0x0030
494 #define OMAP_GPIO_OE 0x0034
495 #define OMAP_GPIO_DATAIN 0x0038
496 #define OMAP_GPIO_DATAOUT 0x003c
497 #define OMAP_GPIO_LEVELDETECT0 0x0040
498 #define OMAP_GPIO_LEVELDETECT1 0x0044
499 #define OMAP_GPIO_RISINGDETECT 0x0048
500 #define OMAP_GPIO_FALLINGDETECT 0x004c
501 #define OMAP_GPIO_DEBOUNCE_EN 0x0050
502 #define OMAP_GPIO_DEBOUNCE_VAL 0x0054
503 #define OMAP_GPIO_CLEARIRQENABLE1 0x0060
504 #define OMAP_GPIO_SETIRQENABLE1 0x0064
505 #define OMAP_GPIO_CLEARWKUENA 0x0080
506 #define OMAP_GPIO_SETWKUENA 0x0084
507 #define OMAP_GPIO_CLEARDATAOUT 0x0090
508 #define OMAP_GPIO_SETDATAOUT 0x0094