2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
12 #include <asm/types.h>
13 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
15 /* Register offsets of common modules */
17 #ifndef __KERNEL_STRICT_NAMES
21 u16 gpmc_nadv_ale; /* 0xC0 */
22 u16 gpmc_noe; /* 0xC2 */
23 u16 gpmc_nwe; /* 0xC4 */
25 u32 status; /* 0x2F0 */
26 u32 gpstatus; /* 0x2F4 */
28 u32 rpubkey_0; /* 0x300 */
29 u32 rpubkey_1; /* 0x304 */
30 u32 rpubkey_2; /* 0x308 */
31 u32 rpubkey_3; /* 0x30C */
32 u32 rpubkey_4; /* 0x310 */
34 u32 randkey_0; /* 0x318 */
35 u32 randkey_1; /* 0x31C */
36 u32 randkey_2; /* 0x320 */
37 u32 randkey_3; /* 0x324 */
39 u32 ctrl_omap_stat; /* 0x44C */
41 #else /* __ASSEMBLY__ */
42 #define CONTROL_STATUS 0x2F0
43 #endif /* __ASSEMBLY__ */
44 #endif /* __KERNEL_STRICT_NAMES */
46 #ifndef __KERNEL_STRICT_NAMES
50 u32 idcode; /* 0x04 */
51 u32 prod_id; /* 0x08 */
52 u32 sku_id; /* 0x0c */
54 u32 die_id_0; /* 0x18 */
55 u32 die_id_1; /* 0x1C */
56 u32 die_id_2; /* 0x20 */
57 u32 die_id_3; /* 0x24 */
59 #endif /* __ASSEMBLY__ */
60 #endif /* __KERNEL_STRICT_NAMES */
63 #define SYSBOOT_MASK 0x1F
66 #define SKUID_CLK_MASK 0xf
67 #define SKUID_CLK_600MHZ 0x0
68 #define SKUID_CLK_720MHZ 0x8
70 #define GPMC_BASE (OMAP34XX_GPMC_BASE)
71 #define GPMC_CONFIG_CS0 0x60
72 #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
74 #ifndef __KERNEL_STRICT_NAMES
76 #define GPMC_CONFIG1 0x00
77 #define GPMC_CONFIG2 0x04
78 #define GPMC_CONFIG3 0x08
79 #define GPMC_CONFIG4 0x0C
80 #define GPMC_CONFIG5 0x10
81 #define GPMC_CONFIG6 0x14
82 #define GPMC_CONFIG7 0x18
83 #endif /* __ASSEMBLY__ */
84 #endif /* __KERNEL_STRICT_NAMES */
87 #define FLASH_BASE 0x10000000 /* NOR flash, */
88 /* aligned to 256 Meg */
89 #define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
90 /* aligned to 64 Meg */
91 #define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
92 /* aligned to 256 Meg */
93 #define DEBUG_BASE 0x08000000 /* debug board */
94 #define NAND_BASE 0x30000000 /* NAND addr */
95 /* (actual size small port) */
96 #define ONENAND_MAP 0x20000000 /* OneNand addr */
97 /* (actual size small port) */
99 #ifndef __KERNEL_STRICT_NAMES
103 u32 sysconfig; /* 0x10 */
105 u32 rg_att0; /* 0x48 */
107 u32 class_arb0; /* 0xD0 */
109 #endif /* __ASSEMBLY__ */
110 #endif /* __KERNEL_STRICT_NAMES */
112 #define BURSTCOMPLETE_GROUP7 (0x1 << 31)
115 #ifndef __KERNEL_STRICT_NAMES
118 u32 mcfg; /* 0x80 || 0xB0 */
119 u32 mr; /* 0x84 || 0xB4 */
121 u32 emr2; /* 0x8C || 0xBC */
123 u32 rfr_ctrl; /* 0x84 || 0xD4 */
124 u32 manual; /* 0xA8 || 0xD8 */
129 u32 ctrla; /* 0x9C || 0xC4 */
130 u32 ctrlb; /* 0xA0 || 0xC8 */
135 u32 sysconfig; /* 0x10 */
136 u32 status; /* 0x14 */
138 u32 cs_cfg; /* 0x40 */
139 u32 sharing; /* 0x44 */
141 u32 dlla_ctrl; /* 0x60 */
142 u32 dlla_status; /* 0x64 */
143 u32 dllb_ctrl; /* 0x68 */
144 u32 dllb_status; /* 0x6C */
145 u32 power; /* 0x70 */
147 struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */
151 typedef struct emif4 {
152 unsigned int emif_mod_id_rev;
153 unsigned int sdram_sts;
154 unsigned int sdram_config;
156 unsigned int sdram_refresh_ctrl;
157 unsigned int sdram_refresh_ctrl_shdw;
158 unsigned int sdram_time1;
159 unsigned int sdram_time1_shdw;
160 unsigned int sdram_time2;
161 unsigned int sdram_time2_shdw;
162 unsigned int sdram_time3;
163 unsigned int sdram_time3_shdw;
164 unsigned char res2[8];
165 unsigned int sdram_pwr_mgmt;
166 unsigned int sdram_pwr_mgmt_shdw;
167 unsigned char res3[32];
168 unsigned int sdram_iodft_tlgc;
169 unsigned char res4[128];
170 unsigned int ddr_phyctrl1;
171 unsigned int ddr_phyctrl1_shdw;
172 unsigned int ddr_phyctrl2;
175 #endif /* __ASSEMBLY__ */
176 #endif /* __KERNEL_STRICT_NAMES */
178 #define DLLPHASE_90 (0x1 << 1)
179 #define LOADDLL (0x1 << 2)
180 #define ENADLL (0x1 << 3)
181 #define DLL_DELAY_MASK 0xFF00
182 #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
184 #define PAGEPOLICY_HIGH (0x1 << 0)
185 #define SRFRONRESET (0x1 << 7)
186 #define PWDNEN (0x1 << 2)
187 #define WAKEUPPROC (0x1 << 26)
189 #define DDR_SDRAM (0x1 << 0)
190 #define DEEPPD (0x1 << 3)
191 #define B32NOT16 (0x1 << 4)
192 #define BANKALLOCATION (0x2 << 6)
193 #define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
194 #define ADDRMUXLEGACY (0x1 << 19)
195 #define CASWIDTH_10BITS (0x5 << 20)
196 #define RASWIDTH_13BITS (0x2 << 24)
197 #define BURSTLENGTH4 (0x2 << 0)
198 #define CASL3 (0x3 << 4)
199 #define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
200 #define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
201 #define ARE_ARCV_1 (0x1 << 0)
202 #define ARCV (0x4e2 << 8) /* Autorefresh count */
203 #define OMAP34XX_SDRC_CS0 0x80000000
204 #define OMAP34XX_SDRC_CS1 0xA0000000
206 #define CMD_PRECHARGE 0x1
207 #define CMD_AUTOREFRESH 0x2
208 #define CMD_ENTR_PWRDOWN 0x3
209 #define CMD_EXIT_PWRDOWN 0x4
210 #define CMD_ENTR_SRFRSH 0x5
211 #define CMD_CKE_HIGH 0x6
212 #define CMD_CKE_LOW 0x7
213 #define SOFTRESET (0x1 << 1)
214 #define SMART_IDLE (0x2 << 3)
215 #define REF_ON_IDLE (0x1 << 6)
218 #ifndef __KERNEL_STRICT_NAMES
244 u32 irqstatus_l[0x4];
245 u32 irqenable_l[0x4];
256 struct dma4_chan chan[32];
259 #endif /*__ASSEMBLY__ */
260 #endif /* __KERNEL_STRICT_NAMES */
262 /* timer regs offsets (32 bit regs) */
264 #ifndef __KERNEL_STRICT_NAMES
267 u32 tidr; /* 0x00 r */
269 u32 tiocp_cfg; /* 0x10 rw */
270 u32 tistat; /* 0x14 r */
271 u32 tisr; /* 0x18 rw */
272 u32 tier; /* 0x1c rw */
273 u32 twer; /* 0x20 rw */
274 u32 tclr; /* 0x24 rw */
275 u32 tcrr; /* 0x28 rw */
276 u32 tldr; /* 0x2c rw */
277 u32 ttgr; /* 0x30 rw */
278 u32 twpc; /* 0x34 r*/
279 u32 tmar; /* 0x38 rw*/
280 u32 tcar1; /* 0x3c r */
281 u32 tcicr; /* 0x40 rw */
282 u32 tcar2; /* 0x44 r */
284 #endif /* __ASSEMBLY__ */
285 #endif /* __KERNEL_STRICT_NAMES */
287 /* enable sys_clk NO-prescale /1 */
288 #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
291 #ifndef __KERNEL_STRICT_NAMES
295 u32 wwps; /* 0x34 r */
297 u32 wspr; /* 0x48 rw */
299 #endif /* __ASSEMBLY__ */
300 #endif /* __KERNEL_STRICT_NAMES */
302 #define WD_UNLOCK1 0xAAAA
303 #define WD_UNLOCK2 0x5555
306 #define PRCM_BASE 0x48004000
308 #ifndef __KERNEL_STRICT_NAMES
311 u32 fclken_iva2; /* 0x00 */
312 u32 clken_pll_iva2; /* 0x04 */
314 u32 idlest_pll_iva2; /* 0x24 */
316 u32 clksel1_pll_iva2 ; /* 0x40 */
317 u32 clksel2_pll_iva2; /* 0x44 */
319 u32 clken_pll_mpu; /* 0x904 */
321 u32 idlest_pll_mpu; /* 0x924 */
323 u32 clksel1_pll_mpu; /* 0x940 */
324 u32 clksel2_pll_mpu; /* 0x944 */
326 u32 fclken1_core; /* 0xa00 */
327 u32 res_fclken2_core;
328 u32 fclken3_core; /* 0xa08 */
330 u32 iclken1_core; /* 0xa10 */
331 u32 iclken2_core; /* 0xa14 */
332 u32 iclken3_core; /* 0xa18 */
334 u32 clksel_core; /* 0xa40 */
336 u32 fclken_gfx; /* 0xb00 */
338 u32 iclken_gfx; /* 0xb10 */
340 u32 clksel_gfx; /* 0xb40 */
342 u32 fclken_wkup; /* 0xc00 */
344 u32 iclken_wkup; /* 0xc10 */
346 u32 idlest_wkup; /* 0xc20 */
348 u32 clksel_wkup; /* 0xc40 */
350 u32 clken_pll; /* 0xd00 */
351 u32 clken2_pll; /* 0xd04 */
353 u32 idlest_ckgen; /* 0xd20 */
354 u32 idlest2_ckgen; /* 0xd24 */
356 u32 clksel1_pll; /* 0xd40 */
357 u32 clksel2_pll; /* 0xd44 */
358 u32 clksel3_pll; /* 0xd48 */
359 u32 clksel4_pll; /* 0xd4c */
360 u32 clksel5_pll; /* 0xd50 */
362 u32 fclken_dss; /* 0xe00 */
364 u32 iclken_dss; /* 0xe10 */
366 u32 clksel_dss; /* 0xe40 */
368 u32 fclken_cam; /* 0xf00 */
370 u32 iclken_cam; /* 0xf10 */
372 u32 clksel_cam; /* 0xf40 */
374 u32 fclken_per; /* 0x1000 */
376 u32 iclken_per; /* 0x1010 */
378 u32 clksel_per; /* 0x1040 */
380 u32 clksel1_emu; /* 0x1140 */
382 u32 fclken_usbhost; /* 0x1400 */
384 u32 iclken_usbhost; /* 0x1410 */
386 #else /* __ASSEMBLY__ */
387 #define CM_CLKSEL_CORE 0x48004a40
388 #define CM_CLKSEL_GFX 0x48004b40
389 #define CM_CLKSEL_WKUP 0x48004c40
390 #define CM_CLKEN_PLL 0x48004d00
391 #define CM_CLKSEL1_PLL 0x48004d40
392 #define CM_CLKSEL1_EMU 0x48005140
393 #endif /* __ASSEMBLY__ */
394 #endif /* __KERNEL_STRICT_NAMES */
396 #define PRM_BASE 0x48306000
398 #ifndef __KERNEL_STRICT_NAMES
402 u32 clksel; /* 0xd40 */
404 u32 rstctrl; /* 0x1250 */
406 u32 clksrc_ctrl; /* 0x1270 */
408 #endif /* __ASSEMBLY__ */
409 #endif /* __KERNEL_STRICT_NAMES */
411 #define PRM_RSTCTRL 0x48307250
412 #define PRM_RSTCTRL_RESET 0x04
413 #define PRM_RSTST 0x48307258
414 #define PRM_RSTST_WARM_RESET_MASK 0x7D2
415 #define SYSCLKDIV_1 (0x1 << 6)
416 #define SYSCLKDIV_2 (0x1 << 7)
418 #define CLKSEL_GPT1 (0x1 << 0)
420 #define EN_GPT1 (0x1 << 0)
421 #define EN_32KSYNC (0x1 << 2)
423 #define ST_WDT2 (0x1 << 5)
425 #define ST_MPU_CLK (0x1 << 0)
427 #define ST_CORE_CLK (0x1 << 0)
429 #define ST_PERIPH_CLK (0x1 << 1)
431 #define ST_IVA2_CLK (0x1 << 0)
433 #define RESETDONE (0x1 << 0)
435 #define TCLR_ST (0x1 << 0)
436 #define TCLR_AR (0x1 << 1)
437 #define TCLR_PRE (0x1 << 5)
440 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
441 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
442 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
443 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
445 #ifndef __KERNEL_STRICT_NAMES
449 u32 req_info_permission_0; /* 0x48 */
451 u32 read_permission_0; /* 0x50 */
453 u32 wirte_permission_0; /* 0x58 */
455 u32 addr_match_1; /* 0x58 */
457 u32 req_info_permission_1; /* 0x68 */
459 u32 addr_match_2; /* 0x80 */
461 #endif /*__ASSEMBLY__ */
462 #endif /* __KERNEL_STRICT_NAMES */
464 /* Permission values for registers -Full fledged permissions to all */
465 #define UNLOCK_1 0xFFFFFFFF
466 #define UNLOCK_2 0x00000000
467 #define UNLOCK_3 0x0000FFFF
472 #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
473 #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
474 #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
477 #define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
479 /* OMAP3 GPIO registers */
480 #define OMAP_GPIO_REVISION 0x0000
481 #define OMAP_GPIO_SYSCONFIG 0x0010
482 #define OMAP_GPIO_SYSSTATUS 0x0014
483 #define OMAP_GPIO_IRQSTATUS1 0x0018
484 #define OMAP_GPIO_IRQSTATUS2 0x0028
485 #define OMAP_GPIO_IRQENABLE2 0x002c
486 #define OMAP_GPIO_IRQENABLE1 0x001c
487 #define OMAP_GPIO_WAKE_EN 0x0020
488 #define OMAP_GPIO_CTRL 0x0030
489 #define OMAP_GPIO_OE 0x0034
490 #define OMAP_GPIO_DATAIN 0x0038
491 #define OMAP_GPIO_DATAOUT 0x003c
492 #define OMAP_GPIO_LEVELDETECT0 0x0040
493 #define OMAP_GPIO_LEVELDETECT1 0x0044
494 #define OMAP_GPIO_RISINGDETECT 0x0048
495 #define OMAP_GPIO_FALLINGDETECT 0x004c
496 #define OMAP_GPIO_DEBOUNCE_EN 0x0050
497 #define OMAP_GPIO_DEBOUNCE_VAL 0x0054
498 #define OMAP_GPIO_CLEARIRQENABLE1 0x0060
499 #define OMAP_GPIO_SETIRQENABLE1 0x0064
500 #define OMAP_GPIO_CLEARWKUENA 0x0080
501 #define OMAP_GPIO_SETWKUENA 0x0084
502 #define OMAP_GPIO_CLEARDATAOUT 0x0090
503 #define OMAP_GPIO_SETDATAOUT 0x0094