2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* Stuff on L3 Interconnect */
30 #define SMX_APE_BASE 0x68000000
33 #define OMAP34XX_GPMC_BASE 0x6E000000
36 #define OMAP34XX_SMS_BASE 0x6C000000
39 #define OMAP34XX_SDRC_BASE 0x6D000000
42 * L4 Peripherals - L4 Wakeup and L4 Core now
44 #define OMAP34XX_CORE_L4_IO_BASE 0x48000000
45 #define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
46 #define OMAP34XX_ID_L4_IO_BASE 0x4830A200
47 #define OMAP34XX_L4_PER 0x49000000
48 #define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
51 #define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
54 /* Signal Integrity Parameter Control Registers */
55 struct control_prog_io {
56 unsigned char res[0x408];
57 unsigned int io2; /* 0x408 */
58 unsigned char res2[0x38];
59 unsigned int io0; /* 0x444 */
60 unsigned int io1; /* 0x448 */
62 #endif /* __ASSEMBLY__ */
64 /* Bit definition for CONTROL_PROG_IO1 */
65 #define PRG_I2C2_PULLUPRESX 0x00000001
68 #define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
69 #define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
70 #define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
72 /* General Purpose Timers */
73 #define OMAP34XX_GPT1 0x48318000
74 #define OMAP34XX_GPT2 0x49032000
75 #define OMAP34XX_GPT3 0x49034000
76 #define OMAP34XX_GPT4 0x49036000
77 #define OMAP34XX_GPT5 0x49038000
78 #define OMAP34XX_GPT6 0x4903A000
79 #define OMAP34XX_GPT7 0x4903C000
80 #define OMAP34XX_GPT8 0x4903E000
81 #define OMAP34XX_GPT9 0x49040000
82 #define OMAP34XX_GPT10 0x48086000
83 #define OMAP34XX_GPT11 0x48088000
84 #define OMAP34XX_GPT12 0x48304000
86 /* WatchDog Timers (1 secure, 3 GP) */
87 #define WD1_BASE 0x4830C000
88 #define WD2_BASE 0x48314000
89 #define WD3_BASE 0x49030000
92 #define SYNC_32KTIMER_BASE 0x48320000
97 unsigned char res[0x10];
98 unsigned int s32k_cr; /* 0x10 */
101 #endif /* __ASSEMBLY__ */
103 /* OMAP3 GPIO registers */
104 #define OMAP34XX_GPIO1_BASE 0x48310000
105 #define OMAP34XX_GPIO2_BASE 0x49050000
106 #define OMAP34XX_GPIO3_BASE 0x49052000
107 #define OMAP34XX_GPIO4_BASE 0x49054000
108 #define OMAP34XX_GPIO5_BASE 0x49056000
109 #define OMAP34XX_GPIO6_BASE 0x49058000
113 unsigned char res1[0x34];
114 unsigned int oe; /* 0x34 */
115 unsigned int datain; /* 0x38 */
116 unsigned char res2[0x54];
117 unsigned int cleardataout; /* 0x90 */
118 unsigned int setdataout; /* 0x94 */
120 #endif /* __ASSEMBLY__ */
122 #define GPIO0 (0x1 << 0)
123 #define GPIO1 (0x1 << 1)
124 #define GPIO2 (0x1 << 2)
125 #define GPIO3 (0x1 << 3)
126 #define GPIO4 (0x1 << 4)
127 #define GPIO5 (0x1 << 5)
128 #define GPIO6 (0x1 << 6)
129 #define GPIO7 (0x1 << 7)
130 #define GPIO8 (0x1 << 8)
131 #define GPIO9 (0x1 << 9)
132 #define GPIO10 (0x1 << 10)
133 #define GPIO11 (0x1 << 11)
134 #define GPIO12 (0x1 << 12)
135 #define GPIO13 (0x1 << 13)
136 #define GPIO14 (0x1 << 14)
137 #define GPIO15 (0x1 << 15)
138 #define GPIO16 (0x1 << 16)
139 #define GPIO17 (0x1 << 17)
140 #define GPIO18 (0x1 << 18)
141 #define GPIO19 (0x1 << 19)
142 #define GPIO20 (0x1 << 20)
143 #define GPIO21 (0x1 << 21)
144 #define GPIO22 (0x1 << 22)
145 #define GPIO23 (0x1 << 23)
146 #define GPIO24 (0x1 << 24)
147 #define GPIO25 (0x1 << 25)
148 #define GPIO26 (0x1 << 26)
149 #define GPIO27 (0x1 << 27)
150 #define GPIO28 (0x1 << 28)
151 #define GPIO29 (0x1 << 29)
152 #define GPIO30 (0x1 << 30)
153 #define GPIO31 (0x1 << 31)
155 /* base address for indirect vectors (internal boot mode) */
156 #define SRAM_OFFSET0 0x40000000
157 #define SRAM_OFFSET1 0x00200000
158 #define SRAM_OFFSET2 0x0000F800
159 #define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
162 #define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */
163 #define OMAP3_PUBLIC_SRAM_END 0x40210000
165 #define LOW_LEVEL_SRAM_STACK 0x4020FFFC
167 /* scratch area - accessible on both EMU and GP */
168 #define OMAP3_PUBLIC_SRAM_SCRATCH_AREA OMAP3_PUBLIC_SRAM_BASE
170 #define DEBUG_LED1 149 /* gpio */
171 #define DEBUG_LED2 150 /* gpio */
173 #define XDR_POP 5 /* package on package part */
174 #define SDR_DISCRETE 4 /* 128M memory SDR module */
175 #define DDR_STACKED 3 /* stacked part on 2422 */
176 #define DDR_COMBO 2 /* combo part on cpu daughter card */
177 #define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
179 #define DDR_100 100 /* type found on most mem d-boards */
180 #define DDR_111 111 /* some combo parts */
181 #define DDR_133 133 /* most combo, some mem d-boards */
182 #define DDR_165 165 /* future parts */
184 #define CPU_3430 0x3430
187 * 343x real hardware:
190 * ES2 onwards, the value maps to contents of IDCODE register [31:28].
192 * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing.
194 #define CPU_3XX_ES10 0
195 #define CPU_3XX_ES20 1
196 #define CPU_3XX_ES21 2
197 #define CPU_3XX_ES30 3
198 #define CPU_3XX_ES31 4
199 #define CPU_3XX_ES312 7
200 #define CPU_3XX_MAX_REV 8
202 #define CPU_3XX_ID_SHIFT 28
204 #define WIDTH_8BIT 0x0000
205 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
210 #define HAWKEYE_OMAP34XX 0xb7ae
211 #define HAWKEYE_AM35XX 0xb868
212 #define HAWKEYE_OMAP36XX 0xb891
214 #define HAWKEYE_SHIFT 12
217 * Define CPU families
219 #define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */
220 #define CPU_AM35XX 0x3500 /* AM35xx devices */
221 #define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */
224 * Control status register values corresponding to cpu variants
226 #define OMAP3503 0x5c00
227 #define OMAP3515 0x1c00
228 #define OMAP3525 0x4c00
229 #define OMAP3530 0x0c00
231 #define AM3505 0x5c00
232 #define AM3517 0x1c00
234 #define OMAP3730 0x0c00
237 * ROM code API related flags
239 #define OMAP3_GP_ROMCODE_API_L2_INVAL 1
240 #define OMAP3_GP_ROMCODE_API_WRITE_ACR 3
243 * EMU device PPA HAL related flags
245 #define OMAP3_EMU_HAL_API_L2_INVAL 40
246 #define OMAP3_EMU_HAL_API_WRITE_ACR 42
248 #define OMAP3_EMU_HAL_START_HAL_CRITICAL 4