3 * Texas Instruments, <www.ti.com>
6 * Aneesh V <aneesh@ti.com>
8 * Derived from OMAP3 work by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
35 #include <asm/types.h>
36 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
39 * L4 Peripherals - L4 Wakeup and L4 Core now
41 #define OMAP44XX_L4_CORE_BASE 0x4A000000
42 #define OMAP44XX_L4_WKUP_BASE 0x4A300000
43 #define OMAP44XX_L4_PER_BASE 0x48000000
46 #define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
47 #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
48 #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
51 #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
52 #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
53 #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
55 /* General Purpose Timers */
56 #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
57 #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
58 #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
60 /* Watchdog Timer2 - MPU watchdog */
61 #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
64 #define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
67 #define OMAP44XX_GPMC_BASE 0x50000000
70 * Hardware Register Details
74 #define WD_UNLOCK1 0xAAAA
75 #define WD_UNLOCK2 0x5555
78 #define TCLR_ST (0x1 << 0)
79 #define TCLR_AR (0x1 << 1)
80 #define TCLR_PRE (0x1 << 5)
87 #define PRM_BASE 0x4A306000
88 #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
90 #define PRM_RSTCTRL PRM_DEVICE_BASE
91 #define PRM_RSTCTRL_RESET 0x01
96 unsigned char res[0x10];
97 unsigned int s32k_cr; /* 0x10 */
100 #endif /* __ASSEMBLY__ */
103 * Non-secure SRAM Addresses
104 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
105 * at 0x40304000(EMU base) so that our code works for both EMU and GP
107 #define NON_SECURE_SRAM_START 0x40304000
108 #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
109 /* base address for indirect vectors (internal boot mode) */
110 #define SRAM_ROM_VECT_BASE 0x4030D000
111 /* Temporary SRAM stack used while low level init is done */
112 #define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
115 * OMAP4 real hardware:
116 * TODO: Change this to the IDCODE in the hw regsiter
118 #define CPU_OMAP4430_ES10 1
119 #define CPU_OMAP4430_ES20 2