3 * Texas Instruments, <www.ti.com>
5 * Aneesh V <aneesh@ti.com>
6 * Sricharan R <r.sricharan@ti.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #ifndef _CLOCKS_OMAP5_H_
27 #define _CLOCKS_OMAP5_H_
29 #include <asm/omap_common.h>
32 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
33 * loop, allow for a minimum of 2 ms wait (in reality the wait will be
34 * much more than that)
36 #define LDELAY 1000000
38 #define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120)
39 #define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140)
40 #define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
41 #define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
43 /* DPLL register offsets */
44 #define CM_CLKMODE_DPLL 0
45 #define CM_IDLEST_DPLL 0x4
46 #define CM_AUTOIDLE_DPLL 0x8
47 #define CM_CLKSEL_DPLL 0xC
49 #define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
52 #define CM_DLL_CTRL_OVERRIDE_SHIFT 0
53 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
54 #define CM_DLL_CTRL_NO_OVERRIDE 0
57 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
58 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
59 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
60 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
61 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
62 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
63 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
64 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
65 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
66 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
67 #define CM_CLKMODE_DPLL_EN_SHIFT 0
68 #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
70 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
71 #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
73 #define DPLL_EN_STOP 1
74 #define DPLL_EN_MN_BYPASS 4
75 #define DPLL_EN_LOW_POWER_BYPASS 5
76 #define DPLL_EN_FAST_RELOCK_BYPASS 6
77 #define DPLL_EN_LOCK 7
79 /* CM_IDLEST_DPLL fields */
80 #define ST_DPLL_CLK_MASK 1
83 #define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
84 #define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
87 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
88 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
89 #define CM_CLKSEL_DPLL_M_SHIFT 8
90 #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
91 #define CM_CLKSEL_DPLL_N_SHIFT 0
92 #define CM_CLKSEL_DPLL_N_MASK 0x7F
93 #define CM_CLKSEL_DCC_EN_SHIFT 22
94 #define CM_CLKSEL_DCC_EN_MASK (1 << 22)
96 #define OMAP4_DPLL_MAX_N 127
99 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
102 #define CLKSEL_CORE_SHIFT 0
103 #define CLKSEL_L3_SHIFT 4
104 #define CLKSEL_L4_SHIFT 8
106 #define CLKSEL_CORE_X2_DIV_1 0
107 #define CLKSEL_L3_CORE_DIV_2 1
108 #define CLKSEL_L4_L3_DIV_2 1
110 /* CM_ABE_PLL_REF_CLKSEL */
111 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
112 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
113 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
114 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
116 /* CM_BYPCLK_DPLL_IVA */
117 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
118 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
120 #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
122 /* CM_SHADOW_FREQ_CONFIG1 */
123 #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
124 #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
125 #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
127 #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
128 #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
130 #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
131 #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
133 /*CM_<clock_domain>__CLKCTRL */
134 #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
135 #define CD_CLKCTRL_CLKTRCTRL_MASK 3
137 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
138 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
139 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
140 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
143 /* CM_<clock_domain>_<module>_CLKCTRL */
144 #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
145 #define MODULE_CLKCTRL_MODULEMODE_MASK 3
146 #define MODULE_CLKCTRL_IDLEST_SHIFT 16
147 #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
149 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
150 #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
151 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
153 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
154 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
155 #define MODULE_CLKCTRL_IDLEST_IDLE 2
156 #define MODULE_CLKCTRL_IDLEST_DISABLED 3
158 /* CM_L4PER_GPIO4_CLKCTRL */
159 #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
161 /* CM_L3INIT_HSMMCn_CLKCTRL */
162 #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
163 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
165 /* CM_WKUP_GPTIMER1_CLKCTRL */
166 #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
168 /* CM_CAM_ISS_CLKCTRL */
169 #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
171 /* CM_DSS_DSS_CLKCTRL */
172 #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
174 /* CM_L3INIT_USBPHY_CLKCTRL */
175 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
177 /* CM_MPU_MPU_CLKCTRL */
178 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
179 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
180 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
181 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
183 /* CM_WKUPAON_SCRM_CLKCTRL */
184 #define OPTFCLKEN_SCRM_PER_SHIFT 9
185 #define OPTFCLKEN_SCRM_PER_MASK (1 << 9)
186 #define OPTFCLKEN_SCRM_CORE_SHIFT 8
187 #define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
189 /* CM_COREAON_IO_SRCOMP_CLKCTRL */
190 #define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
191 #define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
193 /* Clock frequencies */
194 #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
195 #define OMAP_SYS_CLK_IND_38_4_MHZ 6
196 #define OMAP_32K_CLK_FREQ 32768
198 /* PRM_VC_VAL_BYPASS */
199 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
202 #define SMPS_I2C_SLAVE_ADDR 0x12
203 #define SMPS_REG_ADDR_12_MPU 0x23
204 #define SMPS_REG_ADDR_45_IVA 0x2B
205 #define SMPS_REG_ADDR_8_CORE 0x37
207 /* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
211 #define VDD_CORE 1040
213 #define VDD_MPU_LOW 890
214 #define VDD_MM_LOW 890
215 #define VDD_CORE_LOW 890
218 #define VDD_MPU_ES2 1060
219 #define VDD_MM_ES2 1025
220 #define VDD_CORE_ES2 1040
222 #define VDD_MPU_ES2_HIGH 1250
223 #define VDD_MM_ES2_OD 1120
225 #define VDD_MPU_ES2_LOW 880
226 #define VDD_MM_ES2_LOW 880
228 /* Standard offset is 0.5v expressed in uv */
229 #define PALMAS_SMPS_BASE_VOLT_UV 500000
232 #define TPS62361_I2C_SLAVE_ADDR 0x60
233 #define TPS62361_REG_ADDR_SET0 0x0
234 #define TPS62361_REG_ADDR_SET1 0x1
235 #define TPS62361_REG_ADDR_SET2 0x2
236 #define TPS62361_REG_ADDR_SET3 0x3
237 #define TPS62361_REG_ADDR_CTRL 0x4
238 #define TPS62361_REG_ADDR_TEMP 0x5
239 #define TPS62361_REG_ADDR_RMP_CTRL 0x6
240 #define TPS62361_REG_ADDR_CHIP_ID 0x8
241 #define TPS62361_REG_ADDR_CHIP_ID_2 0x9
243 #define TPS62361_BASE_VOLT_MV 500
244 #define TPS62361_VSEL0_GPIO 7
246 /* Defines for DPLL setup */
247 #define DPLL_LOCKED_FREQ_TOLERANCE_0 0
248 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
249 #define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
251 #define DPLL_NO_LOCK 0
254 #endif /* _CLOCKS_OMAP5_H_ */