3 * Texas Instruments, <www.ti.com>
6 * Aneesh V <aneesh@ti.com>
7 * Sricharan R <r.sricharan@ti.com>
9 * SPDX-License-Identifier: GPL-2.0+
15 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
16 #include <asm/types.h>
17 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
20 * L4 Peripherals - L4 Wakeup and L4 Core now
22 #define OMAP54XX_L4_CORE_BASE 0x4A000000
23 #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
24 #define OMAP54XX_L4_PER_BASE 0x48000000
26 #define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
27 #define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF
28 #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
29 #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
32 #define CONTROL_CORE_ID_CODE 0x4A002204
33 #define CONTROL_WKUP_ID_CODE 0x4AE0C204
36 #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
38 #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
42 #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
43 #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
44 #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
45 #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
46 #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
47 #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F
50 #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
51 #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
52 #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
53 #define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000)
55 /* General Purpose Timers */
56 #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
57 #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
58 #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
60 /* Watchdog Timer2 - MPU watchdog */
61 #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
64 #define QSPI_BASE 0x4B300000
67 #define DWC_AHSATA_BASE 0x4A140000
70 * Hardware Register Details
74 #define WD_UNLOCK1 0xAAAA
75 #define WD_UNLOCK2 0x5555
78 #define TCLR_ST (0x1 << 0)
79 #define TCLR_AR (0x1 << 1)
80 #define TCLR_PRE (0x1 << 5)
83 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
84 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
85 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
86 #define CONTROL_EFUSE_2_OVERRIDE 0x00084000
89 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
90 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
91 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
92 #define LPDDR2IO_GR10_WD_MASK (3 << 17)
93 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
96 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
98 #define SDCARD_BIAS_PWRDNZ (1 << 27)
99 #define SDCARD_PWRDNZ (1 << 26)
100 #define SDCARD_BIAS_HIZ_MODE (1 << 25)
101 #define SDCARD_PBIASLITE_VMODE (1 << 21)
106 unsigned char res[0x10];
107 unsigned int s32k_cr; /* 0x10 */
110 #define DEVICE_TYPE_SHIFT 0x6
111 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
112 #define DEVICE_GP 0x3
114 /* Output impedance control */
115 #define ds_120_ohm 0x0
116 #define ds_60_ohm 0x1
117 #define ds_45_ohm 0x2
118 #define ds_30_ohm 0x3
121 /* Slew rate control */
123 #define sc_medium 0x1
128 /* Target capacitance control */
129 #define lb_5_12_pf 0x0
130 #define lb_12_25_pf 0x1
131 #define lb_25_50_pf 0x2
132 #define lb_50_80_pf 0x3
135 #define usb_i_mask 0x7
137 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082
138 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
139 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
140 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
141 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
143 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C
144 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464
145 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631
146 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
147 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
149 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
150 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464
151 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
152 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC
153 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
155 #define EFUSE_1 0x45145100
156 #define EFUSE_2 0x45145100
157 #define EFUSE_3 0x45145100
158 #define EFUSE_4 0x45145100
159 #endif /* __ASSEMBLY__ */
162 * In all cases, the TRM defines the RAM Memory Map for the processor
163 * and indicates the area for the downloaded image. We use all of that
164 * space for download and once up and running may use other parts of the
165 * map for our needs. We set a scratch space that is at the end of the
166 * OMAP5 download area, but within the DRA7xx download area (as it is
167 * much larger) and do not, at this time, make use of the additional
171 #define NON_SECURE_SRAM_START 0x40300000
172 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
174 #define NON_SECURE_SRAM_START 0x40300000
175 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
177 #define SRAM_SCRATCH_SPACE_ADDR 0x4031E000
179 /* base address for indirect vectors (internal boot mode) */
180 #define SRAM_ROM_VECT_BASE 0x4031F000
182 /* CONTROL_SRCOMP_XXX_SIDE */
183 #define OVERRIDE_XS_SHIFT 30
184 #define OVERRIDE_XS_MASK (1 << 30)
185 #define SRCODE_READ_XS_SHIFT 12
186 #define SRCODE_READ_XS_MASK (0xff << 12)
187 #define PWRDWN_XS_SHIFT 11
188 #define PWRDWN_XS_MASK (1 << 11)
189 #define DIVIDE_FACTOR_XS_SHIFT 4
190 #define DIVIDE_FACTOR_XS_MASK (0x7f << 4)
191 #define MULTIPLY_FACTOR_XS_SHIFT 1
192 #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1)
193 #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
194 #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
197 #define OMAP_ABB_SETTLING_TIME 50
198 #define OMAP_ABB_CLOCK_CYCLES 16
200 /* ABB tranxdone mask */
201 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
203 /* ABB efuse masks */
204 #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24)
205 #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29)
206 #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20)
207 #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25)
208 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10)
209 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)
211 /* IO Delay module defines */
212 #define CFG_IO_DELAY_BASE 0x4844A000
213 #define CFG_IO_DELAY_LOCK (CFG_IO_DELAY_BASE + 0x02C)
215 /* CPSW IO Delay registers*/
216 #define CFG_RGMII0_TXCTL (CFG_IO_DELAY_BASE + 0x74C)
217 #define CFG_RGMII0_TXD0 (CFG_IO_DELAY_BASE + 0x758)
218 #define CFG_RGMII0_TXD1 (CFG_IO_DELAY_BASE + 0x764)
219 #define CFG_RGMII0_TXD2 (CFG_IO_DELAY_BASE + 0x770)
220 #define CFG_RGMII0_TXD3 (CFG_IO_DELAY_BASE + 0x77C)
221 #define CFG_VIN2A_D13 (CFG_IO_DELAY_BASE + 0xA7C)
222 #define CFG_VIN2A_D17 (CFG_IO_DELAY_BASE + 0xAAC)
223 #define CFG_VIN2A_D16 (CFG_IO_DELAY_BASE + 0xAA0)
224 #define CFG_VIN2A_D15 (CFG_IO_DELAY_BASE + 0xA94)
225 #define CFG_VIN2A_D14 (CFG_IO_DELAY_BASE + 0xA88)
227 #define CFG_IO_DELAY_UNLOCK_KEY 0x0000AAAA
228 #define CFG_IO_DELAY_LOCK_KEY 0x0000AAAB
229 #define CFG_IO_DELAY_ACCESS_PATTERN 0x00029000
230 #define CFG_IO_DELAY_LOCK_MASK 0x400
233 struct srcomp_params {
245 u32 ctrl_emif_sdram_config_ext;
246 u32 ctrl_emif_sdram_config_ext_final;
247 u32 ctrl_ddr_ctrl_ext_0;
254 #endif /* __ASSEMBLY__ */