2 * Copyright (C) 2012 Renesas Solutions Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 #ifndef __ASM_ARCH_R8A7740_H
20 #define __ASM_ARCH_R8A7740_H
23 * R8A7740 I/O Addresses
26 #define MERAM_BASE 0xE5580000
27 #define DDRP_BASE 0xC12A0000
28 #define HPB_BASE 0xE6000000
29 #define RWDT0_BASE 0xE6020000
30 #define RWDT1_BASE 0xE6030000
31 #define GPIO_BASE 0xE6050000
32 #define CMT1_BASE 0xE6138000
33 #define CPG_BASE 0xE6150000
34 #define SYSC_BASE 0xE6180000
35 #define SDHI0_BASE 0xE6850000
36 #define SDHI1_BASE 0xE6860000
37 #define MMCIF_BASE 0xE6BD0000
38 #define SCIF5_BASE 0xE6CB0000
39 #define SCIF6_BASE 0xE6CC0000
40 #define DBSC_BASE 0xFE400000
41 #define BSC_BASE 0xFEC10000
42 #define I2C0_BASE 0xFFF20000
43 #define I2C1_BASE 0xE6C20000
44 #define TMU_BASE 0xFFF80000
47 #include <asm/types.h>
51 u16 rwtcnt0; /* 0x00 */
52 u16 dummy0; /* 0x02 */
53 u16 rwtcsra0; /* 0x04 */
54 u16 dummy1; /* 0x06 */
55 u16 rwtcsrb0; /* 0x08 */
56 u16 dummy2; /* 0x0A */
59 /* HPB Semaphore Control Registers */
65 u32 dummy0; /* 0x20 */
79 u32 dummy0; /* 0x1c */
85 u32 dummy1; /* 0x34 */
89 u32 dummy2; /* 0x44 */
92 u32 dummy3; /* 0x50 */
94 u32 dummy4[4]; /* 0x58 .. 0x64 */
96 u32 dummy5[5]; /* 0x6c .. 0x7c */
101 u32 dummy6[3]; /* 0x90 .. 0x98 */
104 u32 dummy7; /* 0xa4 */
106 u32 dummy8; /* 0xac */
108 u32 dummy9; /* 0xb4 */
111 u32 dummy10; /* 0xc0 */
114 u32 dummy11[5]; /* 0xcc .. 0xdc */
117 u32 dummy12[10]; /* 0xe8 .. 0x10c */
124 u32 dummy13[2]; /* 0x128 .. 0x12c */
138 u32 dummy0; /* 0x0c */
143 u32 dummy1; /* 0x20 */
146 u32 dummy2; /* 0x2c */
151 u32 dummy3[5]; /* 0x40 .. 0x50 */
154 u32 dummy4[5]; /* 0x5c .. 0x6c */
156 u32 dummy5[7]; /* 0x74 .. 0x8c */
190 u32 dummy6[68]; /* 0x114 .. 0x220 */
193 u32 dummy7; /* 0x22c */
197 #define CS0WCR2 0xFEC10224
198 #define CS2WCR2 0xFEC10228
199 #define CS4WCR2 0xFEC10230
202 struct r8a7740_ddrp {
211 u32 dummy0[50]; /* 0x20 .. 0xe4 */
214 u32 dummy1[2]; /* 0xf0 .. 0xf4 */
218 #define DDRPNCNT 0xE605803C
219 #define DDRVREFCNT 0xE61500EC
222 struct r8a7740_dbsc {
233 u32 dummy1[2]; /* 0x28 .. 0x2c */
235 u32 dummy2[3]; /* 0x34 .. 0x3c */
239 u32 dummy3; /* 0x4c */
257 u32 dummy4[7]; /* 0x94 .. 0xac */
259 u32 dummy5[3]; /* 0xb4 .. 0xbc */
263 u32 dummy6[5]; /* 0xcc .. 0xdc */
268 u32 dummy7; /* 0xf0 */
271 u32 dummy8; /* 0xfc */;
273 u32 dummy9[31]; /* 0x104 .. 0x17C */
275 u32 dummy10[7]; /* 0x184 .. 0x19C */
277 u32 dummy11[39]; /* 0x1A4 .. 0x23C */
280 u32 dummy12[46]; /* 0x248 .. 0x2FC */
287 #endif /* __ASM_ARCH_R8A7740_H */