2 * drivers/mmc/sh-sdhi.h
4 * SD/MMC driver for Reneas rmobile ARM SoCs
6 * Copyright (C) 2013-2014 Renesas Electronics Corporation
7 * Copyright (C) 2008-2009 Renesas Solutions Corp.
9 * SPDX-License-Identifier: GPL-2.0
15 #define SDHI_CMD (0x0000 >> 1)
16 #define SDHI_PORTSEL (0x0004 >> 1)
17 #define SDHI_ARG0 (0x0008 >> 1)
18 #define SDHI_ARG1 (0x000C >> 1)
19 #define SDHI_STOP (0x0010 >> 1)
20 #define SDHI_SECCNT (0x0014 >> 1)
21 #define SDHI_RSP00 (0x0018 >> 1)
22 #define SDHI_RSP01 (0x001C >> 1)
23 #define SDHI_RSP02 (0x0020 >> 1)
24 #define SDHI_RSP03 (0x0024 >> 1)
25 #define SDHI_RSP04 (0x0028 >> 1)
26 #define SDHI_RSP05 (0x002C >> 1)
27 #define SDHI_RSP06 (0x0030 >> 1)
28 #define SDHI_RSP07 (0x0034 >> 1)
29 #define SDHI_INFO1 (0x0038 >> 1)
30 #define SDHI_INFO2 (0x003C >> 1)
31 #define SDHI_INFO1_MASK (0x0040 >> 1)
32 #define SDHI_INFO2_MASK (0x0044 >> 1)
33 #define SDHI_CLK_CTRL (0x0048 >> 1)
34 #define SDHI_SIZE (0x004C >> 1)
35 #define SDHI_OPTION (0x0050 >> 1)
36 #define SDHI_ERR_STS1 (0x0058 >> 1)
37 #define SDHI_ERR_STS2 (0x005C >> 1)
38 #define SDHI_BUF0 (0x0060 >> 1)
39 #define SDHI_SDIO_MODE (0x0068 >> 1)
40 #define SDHI_SDIO_INFO1 (0x006C >> 1)
41 #define SDHI_SDIO_INFO1_MASK (0x0070 >> 1)
42 #define SDHI_CC_EXT_MODE (0x01B0 >> 1)
43 #define SDHI_SOFT_RST (0x01C0 >> 1)
44 #define SDHI_VERSION (0x01C4 >> 1)
45 #define SDHI_HOST_MODE (0x01C8 >> 1)
46 #define SDHI_SDIF_MODE (0x01CC >> 1)
47 #define SDHI_EXT_SWAP (0x01E0 >> 1)
48 #define SDHI_SD_DMACR (0x0324 >> 1)
51 #define CMD_MASK 0x0000ffff
52 #define SDHI_APP 0x0040
53 #define SDHI_SD_APP_SEND_SCR 0x0073
54 #define SDHI_SD_SWITCH 0x1C06
57 #define USE_1PORT (1 << 8) /* 1 port */
60 #define ARG0_MASK 0x0000ffff
61 #define ARG1_MASK 0x0000ffff
64 #define STOP_SEC_ENABLE (1 << 8)
67 #define INFO1_RESP_END (1 << 0)
68 #define INFO1_ACCESS_END (1 << 2)
69 #define INFO1_CARD_RE (1 << 3)
70 #define INFO1_CARD_IN (1 << 4)
71 #define INFO1_ISD0CD (1 << 5)
72 #define INFO1_WRITE_PRO (1 << 7)
73 #define INFO1_DATA3_CARD_RE (1 << 8)
74 #define INFO1_DATA3_CARD_IN (1 << 9)
75 #define INFO1_DATA3 (1 << 10)
78 #define INFO2_CMD_ERROR (1 << 0)
79 #define INFO2_CRC_ERROR (1 << 1)
80 #define INFO2_END_ERROR (1 << 2)
81 #define INFO2_TIMEOUT (1 << 3)
82 #define INFO2_BUF_ILL_WRITE (1 << 4)
83 #define INFO2_BUF_ILL_READ (1 << 5)
84 #define INFO2_RESP_TIMEOUT (1 << 6)
85 #define INFO2_SDDAT0 (1 << 7)
86 #define INFO2_BRE_ENABLE (1 << 8)
87 #define INFO2_BWE_ENABLE (1 << 9)
88 #define INFO2_CBUSY (1 << 14)
89 #define INFO2_ILA (1 << 15)
90 #define INFO2_ALL_ERR (0x807f)
93 #define INFO1M_RESP_END (1 << 0)
94 #define INFO1M_ACCESS_END (1 << 2)
95 #define INFO1M_CARD_RE (1 << 3)
96 #define INFO1M_CARD_IN (1 << 4)
97 #define INFO1M_DATA3_CARD_RE (1 << 8)
98 #define INFO1M_DATA3_CARD_IN (1 << 9)
99 #define INFO1M_ALL (0xffff)
100 #define INFO1M_SET (INFO1M_RESP_END | \
101 INFO1M_ACCESS_END | \
102 INFO1M_DATA3_CARD_RE | \
103 INFO1M_DATA3_CARD_IN)
105 /* SDHI_INFO2_MASK */
106 #define INFO2M_CMD_ERROR (1 << 0)
107 #define INFO2M_CRC_ERROR (1 << 1)
108 #define INFO2M_END_ERROR (1 << 2)
109 #define INFO2M_TIMEOUT (1 << 3)
110 #define INFO2M_BUF_ILL_WRITE (1 << 4)
111 #define INFO2M_BUF_ILL_READ (1 << 5)
112 #define INFO2M_RESP_TIMEOUT (1 << 6)
113 #define INFO2M_BRE_ENABLE (1 << 8)
114 #define INFO2M_BWE_ENABLE (1 << 9)
115 #define INFO2M_ILA (1 << 15)
116 #define INFO2M_ALL (0xffff)
117 #define INFO2M_ALL_ERR (0x807f)
120 #define CLK_ENABLE (1 << 8)
123 #define OPT_BUS_WIDTH_1 (1 << 15) /* bus width = 1 bit */
126 #define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \
128 #define ERR_STS1_CMD_ERROR ((1 << 4) | (1 << 3) | (1 << 2) | \
132 #define ERR_STS2_RES_TIMEOUT (1 << 0)
133 #define ERR_STS2_RES_STOP_TIMEOUT ((1 << 0) | (1 << 1))
134 #define ERR_STS2_SYS_ERROR ((1 << 6) | (1 << 5) | (1 << 4) | \
135 (1 << 3) | (1 << 2) | (1 << 1) | \
139 #define SDIO_MODE_ON (1 << 0)
140 #define SDIO_MODE_OFF (0 << 0)
142 /* SDHI_SDIO_INFO1 */
143 #define SDIO_INFO1_IOIRQ (1 << 0)
144 #define SDIO_INFO1_EXPUB52 (1 << 14)
145 #define SDIO_INFO1_EXWT (1 << 15)
147 /* SDHI_SDIO_INFO1_MASK */
148 #define SDIO_INFO1M_CLEAR ((1 << 1) | (1 << 2))
149 #define SDIO_INFO1M_ON ((1 << 15) | (1 << 14) | (1 << 2) | \
153 #define SET_SWAP ((1 << 6) | (1 << 7)) /* SWAP */
156 #define SOFT_RST_ON (0 << 0)
157 #define SOFT_RST_OFF (1 << 0)
159 #define CLKDEV_SD_DATA 25000000 /* 25 MHz */
160 #define CLKDEV_HS_DATA 50000000 /* 50 MHz */
161 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */
162 #define CLKDEV_INIT 400000 /* 100 - 400 KHz */
165 #define SH_SDHI_QUIRK_16BIT_BUF (1)
166 int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks);
168 #endif /* _SH_SDHI_H */