2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _ASM_ARCH_CLOCK_H
8 #define _ASM_ARCH_CLOCK_H
11 #define RKCLK_PLL_MODE_SLOW 0
12 #define RKCLK_PLL_MODE_NORMAL 1
19 ROCKCHIP_SYSCON_PMUGRF,
20 ROCKCHIP_SYSCON_PMUSGRF,
25 /* Standard Rockchip clock numbers */
37 static inline int rk_pll_id(enum rk_clk_id clk_id)
43 unsigned int glb_srst_fst_value;
44 unsigned int glb_srst_snd_value;
48 * clk_get_divisor() - Calculate the required clock divisior
50 * Given an input rate and a required output_rate, calculate the Rockchip
51 * divisor needed to achieve this.
53 * @input_rate: Input clock rate in Hz
54 * @output_rate: Output clock rate in Hz
55 * @return divisor register value to use
57 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
61 clk_div = input_rate / output_rate;
62 clk_div = (clk_div + 1) & 0xfffe;
68 * rockchip_get_cru() - get a pointer to the clock/reset unit registers
70 * @return pointer to registers, or -ve error on error
72 void *rockchip_get_cru(void);
75 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
77 * @return pointer to registers, or -ve error on error
79 void *rockchip_get_pmucru(void);
84 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
86 int rockchip_get_clk(struct udevice **devp);