2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _ASM_ARCH_CLOCK_H
8 #define _ASM_ARCH_CLOCK_H
11 #define RKCLK_PLL_MODE_SLOW 0
12 #define RKCLK_PLL_MODE_NORMAL 1
19 ROCKCHIP_SYSCON_PMUGRF,
22 /* Standard Rockchip clock numbers */
34 static inline int rk_pll_id(enum rk_clk_id clk_id)
40 * clk_get_divisor() - Calculate the required clock divisior
42 * Given an input rate and a required output_rate, calculate the Rockchip
43 * divisor needed to achieve this.
45 * @input_rate: Input clock rate in Hz
46 * @output_rate: Output clock rate in Hz
47 * @return divisor register value to use
49 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
53 clk_div = input_rate / output_rate;
54 clk_div = (clk_div + 1) & 0xfffe;
60 * rockchip_get_cru() - get a pointer to the clock/reset unit registers
62 * @return pointer to registers, or -ve error on error
64 void *rockchip_get_cru(void);
69 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
71 int rockchip_get_clk(struct udevice **devp);