1 /* SPDX-License-Identifier: GPL-2.0 */
3 * (C) Copyright 2015 Google, Inc
6 #ifndef _ASM_ARCH_CLOCK_H
7 #define _ASM_ARCH_CLOCK_H
10 #define RKCLK_PLL_MODE_SLOW 0
11 #define RKCLK_PLL_MODE_NORMAL 1
18 ROCKCHIP_SYSCON_PMUGRF,
19 ROCKCHIP_SYSCON_PMUSGRF,
24 /* Standard Rockchip clock numbers */
36 static inline int rk_pll_id(enum rk_clk_id clk_id)
42 unsigned int glb_srst_fst_value;
43 unsigned int glb_srst_snd_value;
47 * clk_get_divisor() - Calculate the required clock divisior
49 * Given an input rate and a required output_rate, calculate the Rockchip
50 * divisor needed to achieve this.
52 * @input_rate: Input clock rate in Hz
53 * @output_rate: Output clock rate in Hz
54 * @return divisor register value to use
56 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
60 clk_div = input_rate / output_rate;
61 clk_div = (clk_div + 1) & 0xfffe;
67 * rockchip_get_cru() - get a pointer to the clock/reset unit registers
69 * @return pointer to registers, or -ve error on error
71 void *rockchip_get_cru(void);
74 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
76 * @return pointer to registers, or -ve error on error
78 void *rockchip_get_pmucru(void);
83 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
85 int rockchip_get_clk(struct udevice **devp);
88 * rockchip_reset_bind() - Bind soft reset device as child of clock device
90 * @pdev: clock udevice
91 * @reg_offset: the first offset in cru for softreset registers
92 * @reg_number: the reg numbers of softreset registers
93 * @return 0 success, or error value
95 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);