2 * (C) Copyright 2015 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_CRU_RK3036_H
7 #define _ASM_ARCH_CRU_RK3036_H
11 #define OSC_HZ (24 * 1000 * 1000)
13 #define APLL_HZ (600 * 1000000)
14 #define GPLL_HZ (594 * 1000000)
16 #define CORE_PERI_HZ 150000000
17 #define CORE_ACLK_HZ 300000000
19 #define CPU_ACLK_HZ 150000000
20 #define CPU_HCLK_HZ 300000000
21 #define CPU_PCLK_HZ 300000000
23 #define PERI_ACLK_HZ 148500000
24 #define PERI_HCLK_HZ 148500000
25 #define PERI_PCLK_HZ 74250000
27 /* Private data for the clock driver - used by rockchip_get_cru() */
28 struct rk3036_clk_priv {
29 struct rk3036_cru *cru;
40 unsigned int cru_mode_con;
41 unsigned int cru_clksel_con[35];
42 unsigned int cru_clkgate_con[11];
43 unsigned int reserved;
44 unsigned int cru_glb_srst_fst_value;
45 unsigned int cru_glb_srst_snd_value;
46 unsigned int reserved1[2];
47 unsigned int cru_softrst_con[9];
48 unsigned int cru_misc_con;
49 unsigned int reserved2[2];
50 unsigned int cru_glb_cnt_th;
51 unsigned int cru_sdmmc_con[2];
52 unsigned int cru_sdio_con[2];
53 unsigned int cru_emmc_con[2];
54 unsigned int reserved3;
55 unsigned int cru_rst_st;
56 unsigned int reserved4[0x23];
57 unsigned int cru_pll_mask_con;
59 check_member(rk3036_cru, cru_pll_mask_con, 0x01f0);
71 PLL_POSTDIV1_MASK = 7,
72 PLL_POSTDIV1_SHIFT = 12,
73 PLL_FBDIV_MASK = 0xfff,
79 PLL_LOCK_STATUS_MASK = 1,
80 PLL_LOCK_STATUS_SHIFT = 10,
81 PLL_POSTDIV2_MASK = 7,
82 PLL_POSTDIV2_SHIFT = 6,
83 PLL_REFDIV_MASK = 0x3f,
102 /* CRU_CLK_SEL0_CON */
103 CPU_CLK_PLL_SEL_MASK = 3,
104 CPU_CLK_PLL_SEL_SHIFT = 14,
105 CPU_CLK_PLL_SEL_APLL = 0,
106 CPU_CLK_PLL_SEL_DPLL,
107 CPU_CLK_PLL_SEL_GPLL,
108 ACLK_CPU_DIV_MASK = 0x1f,
109 ACLK_CPU_DIV_SHIFT = 8,
110 CORE_CLK_PLL_SEL_MASK = 1,
111 CORE_CLK_PLL_SEL_SHIFT = 7,
112 CORE_CLK_PLL_SEL_APLL = 0,
113 CORE_CLK_PLL_SEL_GPLL,
114 CORE_DIV_CON_MASK = 0x1f,
115 CORE_DIV_CON_SHIFT = 0,
117 /* CRU_CLK_SEL1_CON */
118 CPU_PCLK_DIV_MASK = 7,
119 CPU_PCLK_DIV_SHIFT = 12,
120 CPU_HCLK_DIV_MASK = 3,
121 CPU_HCLK_DIV_SHIFT = 8,
122 CORE_ACLK_DIV_MASK = 7,
123 CORE_ACLK_DIV_SHIFT = 4,
124 CORE_PERI_DIV_MASK = 0xf,
125 CORE_PERI_DIV_SHIFT = 0,
127 /* CRU_CLKSEL10_CON */
128 PERI_PLL_SEL_MASK = 3,
129 PERI_PLL_SEL_SHIFT = 14,
133 PERI_PCLK_DIV_MASK = 3,
134 PERI_PCLK_DIV_SHIFT = 12,
135 PERI_HCLK_DIV_MASK = 3,
136 PERI_HCLK_DIV_SHIFT = 8,
137 PERI_ACLK_DIV_MASK = 0x1f,
138 PERI_ACLK_DIV_SHIFT = 0,
140 /* CRU_CLKSEL11_CON */
141 SDIO_DIV_MASK = 0x7f,
143 MMC0_DIV_MASK = 0x7f,
146 /* CRU_CLKSEL12_CON */
165 EMMC_DIV_MASK = 0x7f,
168 /* CRU_SOFTRST5_CON */
169 DDRCTRL_PSRST_SHIFT = 11,
170 DDRCTRL_SRST_SHIFT = 10,
171 DDRPHY_PSRST_SHIFT = 9,
172 DDRPHY_SRST_SHIFT = 8,