1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2015 Rockchip Electronics Co., Ltd
5 #ifndef _ASM_ARCH_CRU_RK3036_H
6 #define _ASM_ARCH_CRU_RK3036_H
10 #define OSC_HZ (24 * 1000 * 1000)
12 #define APLL_HZ (600 * 1000000)
13 #define GPLL_HZ (594 * 1000000)
15 #define CORE_PERI_HZ 150000000
16 #define CORE_ACLK_HZ 300000000
18 #define BUS_ACLK_HZ 148500000
19 #define BUS_HCLK_HZ 148500000
20 #define BUS_PCLK_HZ 74250000
22 #define PERI_ACLK_HZ 148500000
23 #define PERI_HCLK_HZ 148500000
24 #define PERI_PCLK_HZ 74250000
26 /* Private data for the clock driver - used by rockchip_get_cru() */
27 struct rk3036_clk_priv {
28 struct rk3036_cru *cru;
39 unsigned int cru_mode_con;
40 unsigned int cru_clksel_con[35];
41 unsigned int cru_clkgate_con[11];
42 unsigned int reserved;
43 unsigned int cru_glb_srst_fst_value;
44 unsigned int cru_glb_srst_snd_value;
45 unsigned int reserved1[2];
46 unsigned int cru_softrst_con[9];
47 unsigned int cru_misc_con;
48 unsigned int reserved2[2];
49 unsigned int cru_glb_cnt_th;
50 unsigned int cru_sdmmc_con[2];
51 unsigned int cru_sdio_con[2];
52 unsigned int cru_emmc_con[2];
53 unsigned int reserved3;
54 unsigned int cru_rst_st;
55 unsigned int reserved4[0x23];
56 unsigned int cru_pll_mask_con;
58 check_member(rk3036_cru, cru_pll_mask_con, 0x01f0);
70 PLL_POSTDIV1_SHIFT = 12,
71 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
73 PLL_FBDIV_MASK = 0xfff,
78 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
79 PLL_LOCK_STATUS_SHIFT = 10,
80 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
81 PLL_POSTDIV2_SHIFT = 6,
82 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
84 PLL_REFDIV_MASK = 0x3f,
88 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
93 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
97 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
101 /* CRU_CLK_SEL0_CON */
102 BUS_ACLK_PLL_SEL_SHIFT = 14,
103 BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
104 BUS_ACLK_PLL_SEL_APLL = 0,
105 BUS_ACLK_PLL_SEL_DPLL,
106 BUS_ACLK_PLL_SEL_GPLL,
107 BUS_ACLK_DIV_SHIFT = 8,
108 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
109 CORE_CLK_PLL_SEL_SHIFT = 7,
110 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
111 CORE_CLK_PLL_SEL_APLL = 0,
112 CORE_CLK_PLL_SEL_GPLL,
113 CORE_DIV_CON_SHIFT = 0,
114 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
116 /* CRU_CLK_SEL1_CON */
117 BUS_PCLK_DIV_SHIFT = 12,
118 BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
119 BUS_HCLK_DIV_SHIFT = 8,
120 BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
121 CORE_ACLK_DIV_SHIFT = 4,
122 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
123 CORE_PERI_DIV_SHIFT = 0,
124 CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
126 /* CRU_CLKSEL10_CON */
127 PERI_PLL_SEL_SHIFT = 14,
128 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
132 PERI_PCLK_DIV_SHIFT = 12,
133 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
134 PERI_HCLK_DIV_SHIFT = 8,
135 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
136 PERI_ACLK_DIV_SHIFT = 0,
137 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
139 /* CRU_CLKSEL11_CON */
141 SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT,
143 MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT,
145 /* CRU_CLKSEL12_CON */
147 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
153 SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT,
159 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
165 EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT,
167 /* CRU_SOFTRST5_CON */
168 DDRCTRL_PSRST_SHIFT = 11,
169 DDRCTRL_SRST_SHIFT = 10,
170 DDRPHY_PSRST_SHIFT = 9,
171 DDRPHY_SRST_SHIFT = 8,