2 * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_CRU_RK3188_H
7 #define _ASM_ARCH_CRU_RK3188_H
9 #define OSC_HZ (24 * 1000 * 1000)
11 #define APLL_HZ (1608 * 1000000)
12 #define APLL_SAFE_HZ (600 * 1000000)
13 #define GPLL_HZ (594 * 1000000)
14 #define CPLL_HZ (384 * 1000000)
16 /* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
17 #define CPU_ACLK_HZ 297000000
18 #define CPU_HCLK_HZ 148500000
19 #define CPU_PCLK_HZ 74250000
20 #define CPU_H2P_HZ 74250000
22 #define PERI_ACLK_HZ 148500000
23 #define PERI_HCLK_HZ 148500000
24 #define PERI_PCLK_HZ 74250000
26 /* Private data for the clock driver - used by rockchip_get_cru() */
27 struct rk3188_clk_priv {
28 struct rk3188_grf *grf;
29 struct rk3188_cru *cru;
42 u32 cru_clksel_con[35];
43 u32 cru_clkgate_con[10];
45 u32 cru_glb_srst_fst_value;
46 u32 cru_glb_srst_snd_value;
48 u32 cru_softrst_con[9];
53 check_member(rk3188_cru, cru_glb_cnt_th, 0x0140);
57 /* a9_core_div: core = core_src / (a9_core_div + 1) */
58 A9_CORE_DIV_SHIFT = 9,
59 A9_CORE_DIV_MASK = 0x1f,
62 CORE_PLL_SELECT_APLL = 0,
65 /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
66 CORE_PERI_DIV_SHIFT = 6,
67 CORE_PERI_DIV_MASK = 3,
69 /* aclk_cpu pll selection */
70 CPU_ACLK_PLL_SHIFT = 5,
71 CPU_ACLK_PLL_MASK = 1,
72 CPU_ACLK_PLL_SELECT_APLL = 0,
73 CPU_ACLK_PLL_SELECT_GPLL,
75 /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
77 A9_CPU_DIV_MASK = 0x1f,
82 /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
83 AHB2APB_DIV_SHIFT = 14,
86 /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
87 CPU_PCLK_DIV_SHIFT = 12,
88 CPU_PCLK_DIV_MASK = 3,
90 /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
91 CPU_HCLK_DIV_SHIFT = 8,
92 CPU_HCLK_DIV_MASK = 3,
94 /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
95 CORE_ACLK_DIV_SHIFT = 3,
96 CORE_ACLK_DIV_MASK = 7,
99 /* CRU_CLKSEL10_CON */
101 PERI_SEL_PLL_MASK = 1,
102 PERI_SEL_PLL_SHIFT = 15,
106 /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
107 PERI_PCLK_DIV_SHIFT = 12,
108 PERI_PCLK_DIV_MASK = 3,
110 /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
111 PERI_HCLK_DIV_SHIFT = 8,
112 PERI_HCLK_DIV_MASK = 3,
114 /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
115 PERI_ACLK_DIV_SHIFT = 0,
116 PERI_ACLK_DIV_MASK = 0x1f,
118 /* CRU_CLKSEL11_CON */
120 HSICPHY_DIV_SHIFT = 8,
121 HSICPHY_DIV_MASK = 0x3f,
124 MMC0_DIV_MASK = 0x3f,
127 /* CRU_CLKSEL12_CON */
131 UART_PLL_SELECT_GENERAL = 0,
132 UART_PLL_SELECT_CODEC,
135 EMMC_DIV_MASK = 0x3f,
138 SDIO_DIV_MASK = 0x3f,
141 /* CRU_CLKSEL25_CON */
144 SPI1_DIV_MASK = 0x7f,
147 SPI0_DIV_MASK = 0x7f,
152 GPLL_MODE_SHIFT = 12,