1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
5 #ifndef _ASM_ARCH_CRU_RK3188_H
6 #define _ASM_ARCH_CRU_RK3188_H
8 #define OSC_HZ (24 * 1000 * 1000)
10 #define APLL_HZ (1608 * 1000000)
11 #define APLL_SAFE_HZ (600 * 1000000)
12 #define GPLL_HZ (594 * 1000000)
13 #define CPLL_HZ (384 * 1000000)
15 /* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
16 #define CPU_ACLK_HZ 297000000
17 #define CPU_HCLK_HZ 148500000
18 #define CPU_PCLK_HZ 74250000
19 #define CPU_H2P_HZ 74250000
21 #define PERI_ACLK_HZ 148500000
22 #define PERI_HCLK_HZ 148500000
23 #define PERI_PCLK_HZ 74250000
25 /* Private data for the clock driver - used by rockchip_get_cru() */
26 struct rk3188_clk_priv {
27 struct rk3188_grf *grf;
28 struct rk3188_cru *cru;
41 u32 cru_clksel_con[35];
42 u32 cru_clkgate_con[10];
44 u32 cru_glb_srst_fst_value;
45 u32 cru_glb_srst_snd_value;
47 u32 cru_softrst_con[9];
52 check_member(rk3188_cru, cru_glb_cnt_th, 0x0140);
56 /* a9_core_div: core = core_src / (a9_core_div + 1) */
57 A9_CORE_DIV_SHIFT = 9,
58 A9_CORE_DIV_MASK = 0x1f,
61 CORE_PLL_SELECT_APLL = 0,
64 /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
65 CORE_PERI_DIV_SHIFT = 6,
66 CORE_PERI_DIV_MASK = 3,
68 /* aclk_cpu pll selection */
69 CPU_ACLK_PLL_SHIFT = 5,
70 CPU_ACLK_PLL_MASK = 1,
71 CPU_ACLK_PLL_SELECT_APLL = 0,
72 CPU_ACLK_PLL_SELECT_GPLL,
74 /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
76 A9_CPU_DIV_MASK = 0x1f,
81 /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
82 AHB2APB_DIV_SHIFT = 14,
85 /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
86 CPU_PCLK_DIV_SHIFT = 12,
87 CPU_PCLK_DIV_MASK = 3,
89 /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
90 CPU_HCLK_DIV_SHIFT = 8,
91 CPU_HCLK_DIV_MASK = 3,
93 /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
94 CORE_ACLK_DIV_SHIFT = 3,
95 CORE_ACLK_DIV_MASK = 7,
98 /* CRU_CLKSEL10_CON */
100 PERI_SEL_PLL_MASK = 1,
101 PERI_SEL_PLL_SHIFT = 15,
105 /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
106 PERI_PCLK_DIV_SHIFT = 12,
107 PERI_PCLK_DIV_MASK = 3,
109 /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
110 PERI_HCLK_DIV_SHIFT = 8,
111 PERI_HCLK_DIV_MASK = 3,
113 /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
114 PERI_ACLK_DIV_SHIFT = 0,
115 PERI_ACLK_DIV_MASK = 0x1f,
117 /* CRU_CLKSEL11_CON */
119 HSICPHY_DIV_SHIFT = 8,
120 HSICPHY_DIV_MASK = 0x3f,
123 MMC0_DIV_MASK = 0x3f,
126 /* CRU_CLKSEL12_CON */
130 UART_PLL_SELECT_GENERAL = 0,
131 UART_PLL_SELECT_CODEC,
134 EMMC_DIV_MASK = 0x3f,
137 SDIO_DIV_MASK = 0x3f,
140 /* CRU_CLKSEL25_CON */
143 SPI1_DIV_MASK = 0x7f,
146 SPI0_DIV_MASK = 0x7f,
151 GPLL_MODE_SHIFT = 12,