git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-rockchip/cru_rk3188.h

   1 /*
   2  * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef _ASM_ARCH_CRU_RK3188_H
   7 #define _ASM_ARCH_CRU_RK3188_H
   8
   9 #define OSC_HZ          (24 * 1000 * 1000)
  10
  11 #define APLL_HZ         (1608 * 1000000)
  12 #define APLL_SAFE_HZ    (600 * 1000000)
  13 #define GPLL_HZ         (594 * 1000000)
  14 #define CPLL_HZ         (384 * 1000000)
  15
  16 /* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
  17 #define CPU_ACLK_HZ     297000000
  18 #define CPU_HCLK_HZ     148500000
  19 #define CPU_PCLK_HZ     74250000
  20 #define CPU_H2P_HZ      74250000
  21
  22 #define PERI_ACLK_HZ    148500000
  23 #define PERI_HCLK_HZ    148500000
  24 #define PERI_PCLK_HZ    74250000
  25
  26 /* Private data for the clock driver - used by rockchip_get_cru() */
  27 struct rk3188_clk_priv {
  28         struct rk3188_grf *grf;
  29         struct rk3188_cru *cru;
  30         ulong rate;
  31         bool has_bwadj;
  32 };
  33
  34 struct rk3188_cru {
  35         struct rk3188_pll {
  36                 u32 con0;
  37                 u32 con1;
  38                 u32 con2;
  39                 u32 con3;
  40         } pll[4];
  41         u32 cru_mode_con;
  42         u32 cru_clksel_con[35];
  43         u32 cru_clkgate_con[10];
  44         u32 reserved1[2];
  45         u32 cru_glb_srst_fst_value;
  46         u32 cru_glb_srst_snd_value;
  47         u32 reserved2[2];
  48         u32 cru_softrst_con[9];
  49         u32 cru_misc_con;
  50         u32 reserved3[2];
  51         u32 cru_glb_cnt_th;
  52 };
  53 check_member(rk3188_cru, cru_glb_cnt_th, 0x0140);
  54
  55 /* CRU_CLKSEL0_CON */
  56 enum {
  57         /* a9_core_div: core = core_src / (a9_core_div + 1) */
  58         A9_CORE_DIV_SHIFT       = 9,
  59         A9_CORE_DIV_MASK        = 0x1f,
  60         CORE_PLL_SHIFT          = 8,
  61         CORE_PLL_MASK           = 1,
  62         CORE_PLL_SELECT_APLL    = 0,
  63         CORE_PLL_SELECT_GPLL,
  64
  65         /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
  66         CORE_PERI_DIV_SHIFT     = 6,
  67         CORE_PERI_DIV_MASK      = 3,
  68
  69         /* aclk_cpu pll selection */
  70         CPU_ACLK_PLL_SHIFT      = 5,
  71         CPU_ACLK_PLL_MASK       = 1,
  72         CPU_ACLK_PLL_SELECT_APLL        = 0,
  73         CPU_ACLK_PLL_SELECT_GPLL,
  74
  75         /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
  76         A9_CPU_DIV_SHIFT        = 0,
  77         A9_CPU_DIV_MASK         = 0x1f,
  78 };
  79
  80 /* CRU_CLKSEL1_CON */
  81 enum {
  82         /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
  83         AHB2APB_DIV_SHIFT       = 14,
  84         AHB2APB_DIV_MASK        = 3,
  85
  86         /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
  87         CPU_PCLK_DIV_SHIFT      = 12,
  88         CPU_PCLK_DIV_MASK       = 3,
  89
  90         /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
  91         CPU_HCLK_DIV_SHIFT      = 8,
  92         CPU_HCLK_DIV_MASK       = 3,
  93
  94         /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
  95         CORE_ACLK_DIV_SHIFT     = 3,
  96         CORE_ACLK_DIV_MASK      = 7,
  97 };
  98
  99 /* CRU_CLKSEL10_CON */
 100 enum {
 101         PERI_SEL_PLL_MASK       = 1,
 102         PERI_SEL_PLL_SHIFT      = 15,
 103         PERI_SEL_CPLL           = 0,
 104         PERI_SEL_GPLL,
 105
 106         /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
 107         PERI_PCLK_DIV_SHIFT     = 12,
 108         PERI_PCLK_DIV_MASK      = 3,
 109
 110         /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
 111         PERI_HCLK_DIV_SHIFT     = 8,
 112         PERI_HCLK_DIV_MASK      = 3,
 113
 114         /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
 115         PERI_ACLK_DIV_SHIFT     = 0,
 116         PERI_ACLK_DIV_MASK      = 0x1f,
 117 };
 118 /* CRU_CLKSEL11_CON */
 119 enum {
 120         HSICPHY_DIV_SHIFT       = 8,
 121         HSICPHY_DIV_MASK        = 0x3f,
 122
 123         MMC0_DIV_SHIFT          = 0,
 124         MMC0_DIV_MASK           = 0x3f,
 125 };
 126
 127 /* CRU_CLKSEL12_CON */
 128 enum {
 129         UART_PLL_SHIFT          = 15,
 130         UART_PLL_MASK           = 1,
 131         UART_PLL_SELECT_GENERAL = 0,
 132         UART_PLL_SELECT_CODEC,
 133
 134         EMMC_DIV_SHIFT          = 8,
 135         EMMC_DIV_MASK           = 0x3f,
 136
 137         SDIO_DIV_SHIFT          = 0,
 138         SDIO_DIV_MASK           = 0x3f,
 139 };
 140
 141 /* CRU_CLKSEL25_CON */
 142 enum {
 143         SPI1_DIV_SHIFT          = 8,
 144         SPI1_DIV_MASK           = 0x7f,
 145
 146         SPI0_DIV_SHIFT          = 0,
 147         SPI0_DIV_MASK           = 0x7f,
 148 };
 149
 150 /* CRU_MODE_CON */
 151 enum {
 152         GPLL_MODE_SHIFT         = 12,
 153         GPLL_MODE_MASK          = 3,
 154         GPLL_MODE_SLOW          = 0,
 155         GPLL_MODE_NORMAL,
 156         GPLL_MODE_DEEP,
 157
 158         CPLL_MODE_SHIFT         = 8,
 159         CPLL_MODE_MASK          = 3,
 160         CPLL_MODE_SLOW          = 0,
 161         CPLL_MODE_NORMAL,
 162         CPLL_MODE_DEEP,
 163
 164         DPLL_MODE_SHIFT         = 4,
 165         DPLL_MODE_MASK          = 3,
 166         DPLL_MODE_SLOW          = 0,
 167         DPLL_MODE_NORMAL,
 168         DPLL_MODE_DEEP,
 169
 170         APLL_MODE_SHIFT         = 0,
 171         APLL_MODE_MASK          = 3,
 172         APLL_MODE_SLOW          = 0,
 173         APLL_MODE_NORMAL,
 174         APLL_MODE_DEEP,
 175 };
 176
 177 /* CRU_APLL_CON0 */
 178 enum {
 179         CLKR_SHIFT              = 8,
 180         CLKR_MASK               = 0x3f,
 181
 182         CLKOD_SHIFT             = 0,
 183         CLKOD_MASK              = 0x3f,
 184 };
 185
 186 /* CRU_APLL_CON1 */
 187 enum {
 188         CLKF_SHIFT              = 0,
 189         CLKF_MASK               = 0x1fff,
 190 };
 191
 192 #endif