1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2015 Google, Inc
5 * (C) Copyright 2008-2014 Rockchip Electronics
6 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
8 #ifndef _ASM_ARCH_CRU_RK3288_H
9 #define _ASM_ARCH_CRU_RK3288_H
11 #define OSC_HZ (24 * 1000 * 1000)
13 #define APLL_HZ (1800 * 1000000)
14 #define GPLL_HZ (594 * 1000000)
15 #define CPLL_HZ (384 * 1000000)
16 #define NPLL_HZ (384 * 1000000)
18 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
19 #define PD_BUS_ACLK_HZ 297000000
20 #define PD_BUS_HCLK_HZ 148500000
21 #define PD_BUS_PCLK_HZ 74250000
23 #define PERI_ACLK_HZ 148500000
24 #define PERI_HCLK_HZ 148500000
25 #define PERI_PCLK_HZ 74250000
27 /* Private data for the clock driver - used by rockchip_get_cru() */
28 struct rk3288_clk_priv {
29 struct rk3288_grf *grf;
30 struct rk3288_cru *cru;
43 u32 cru_clksel_con[43];
45 u32 cru_clkgate_con[19];
47 u32 cru_glb_srst_fst_value;
48 u32 cru_glb_srst_snd_value;
49 u32 cru_softrst_con[12];
61 check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
63 /* CRU_CLKSEL11_CON */
65 HSICPHY_DIV_SHIFT = 8,
66 HSICPHY_DIV_MASK = 0x3f << HSICPHY_DIV_SHIFT,
69 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
70 MMC0_PLL_SELECT_CODEC = 0,
71 MMC0_PLL_SELECT_GENERAL,
72 MMC0_PLL_SELECT_24MHZ,
75 MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
78 /* CRU_CLKSEL12_CON */
81 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
82 EMMC_PLL_SELECT_CODEC = 0,
83 EMMC_PLL_SELECT_GENERAL,
84 EMMC_PLL_SELECT_24MHZ,
87 EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT,
90 SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT,
91 SDIO0_PLL_SELECT_CODEC = 0,
92 SDIO0_PLL_SELECT_GENERAL,
93 SDIO0_PLL_SELECT_24MHZ,
96 SDIO0_DIV_MASK = 0x3f << SDIO0_DIV_SHIFT,
99 /* CRU_CLKSEL21_CON */
101 MAC_DIV_CON_SHIFT = 0xf,
102 MAC_DIV_CON_MASK = 0x1f << MAC_DIV_CON_SHIFT,
104 RMII_EXTCLK_SHIFT = 4,
105 RMII_EXTCLK_MASK = 1 << RMII_EXTCLK_SHIFT,
106 RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
107 RMII_EXTCLK_SELECT_EXT_CLK = 1,
110 EMAC_PLL_MASK = 0x3 << EMAC_PLL_SHIFT,
111 EMAC_PLL_SELECT_NEW = 0x0,
112 EMAC_PLL_SELECT_CODEC = 0x1,
113 EMAC_PLL_SELECT_GENERAL = 0x2,
116 /* CRU_CLKSEL25_CON */
118 SPI1_PLL_SHIFT = 0xf,
119 SPI1_PLL_MASK = 1 << SPI1_PLL_SHIFT,
120 SPI1_PLL_SELECT_CODEC = 0,
121 SPI1_PLL_SELECT_GENERAL,
124 SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT,
127 SPI0_PLL_MASK = 1 << SPI0_PLL_SHIFT,
128 SPI0_PLL_SELECT_CODEC = 0,
129 SPI0_PLL_SELECT_GENERAL,
132 SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT,
135 /* CRU_CLKSEL37_CON */
137 PCLK_CORE_DBG_DIV_SHIFT = 9,
138 PCLK_CORE_DBG_DIV_MASK = 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
140 ATCLK_CORE_DIV_CON_SHIFT = 4,
141 ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
143 CLK_L2RAM_DIV_SHIFT = 0,
144 CLK_L2RAM_DIV_MASK = 7 << CLK_L2RAM_DIV_SHIFT,
147 /* CRU_CLKSEL39_CON */
149 ACLK_HEVC_PLL_SHIFT = 0xe,
150 ACLK_HEVC_PLL_MASK = 3 << ACLK_HEVC_PLL_SHIFT,
151 ACLK_HEVC_PLL_SELECT_CODEC = 0,
152 ACLK_HEVC_PLL_SELECT_GENERAL,
153 ACLK_HEVC_PLL_SELECT_NEW,
155 ACLK_HEVC_DIV_SHIFT = 8,
156 ACLK_HEVC_DIV_MASK = 0x1f << ACLK_HEVC_DIV_SHIFT,
159 SPI2_PLL_MASK = 1 << SPI2_PLL_SHIFT,
160 SPI2_PLL_SELECT_CODEC = 0,
161 SPI2_PLL_SELECT_GENERAL,
164 SPI2_DIV_MASK = 0x7f << SPI2_DIV_SHIFT,
171 NPLL_MODE_SHIFT = 0xe,
172 NPLL_MODE_MASK = CRU_MODE_MASK << NPLL_MODE_SHIFT,
177 GPLL_MODE_SHIFT = 0xc,
178 GPLL_MODE_MASK = CRU_MODE_MASK << GPLL_MODE_SHIFT,
184 CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT,
190 DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT,
196 APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT,
205 CLKR_MASK = 0x3f << CLKR_SHIFT,
208 CLKOD_MASK = 0xf << CLKOD_SHIFT,
214 LOCK_MASK = 1 << LOCK_SHIFT,
219 CLKF_MASK = 0x1fff << CLKF_SHIFT,
225 FST_GLB_RST_ST = BIT(0),
226 SND_GLB_RST_ST = BIT(1),
227 FST_GLB_TSADC_RST_ST = BIT(2),
228 SND_GLB_TSADC_RST_ST = BIT(3),
229 FST_GLB_WDT_RST_ST = BIT(4),
230 SND_GLB_WDT_RST_ST = BIT(5),
231 GLB_RST_ST_MASK = GENMASK(5, 0),