2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_CRU_RK3368_H
7 #define _ASM_ARCH_CRU_RK3368_H
12 /* RK3368 clock numbers */
30 unsigned int reserved[0x28];
31 unsigned int clksel_con[56];
32 unsigned int reserved1[8];
33 unsigned int clkgate_con[25];
34 unsigned int reserved2[7];
35 unsigned int glb_srst_fst_val;
36 unsigned int glb_srst_snd_val;
37 unsigned int reserved3[0x1e];
38 unsigned int softrst_con[15];
39 unsigned int reserved4[0x11];
40 unsigned int misc_con;
41 unsigned int glb_cnt_th;
42 unsigned int glb_rst_con;
43 unsigned int glb_rst_st;
44 unsigned int reserved5[0x1c];
45 unsigned int sdmmc_con[2];
46 unsigned int sdio0_con[2];
47 unsigned int sdio1_con[2];
48 unsigned int emmc_con[2];
50 check_member(rk3368_cru, emmc_con[1], 0x41c);
52 struct rk3368_clk_priv {
53 struct rk3368_cru *cru;
59 PLL_NR_MASK = GENMASK(13, 8),
61 PLL_OD_MASK = GENMASK(3, 0),
64 PLL_LOCK_STA = BIT(31),
66 PLL_NF_MASK = GENMASK(12, 0),
70 PLL_BWADJ_MASK = GENMASK(11, 0),
74 PLL_MODE_MASK = GENMASK(9, 8),
77 PLL_MODE_DEEP_SLOW = 3,
80 PLL_RESET_MASK = GENMASK(5, 5),
83 MCU_STCLK_DIV_SHIFT = 8,
84 MCU_STCLK_DIV_MASK = GENMASK(10, 8),
85 MCU_PLL_SEL_SHIFT = 7,
86 MCU_PLL_SEL_MASK = BIT(7),
89 MCU_CLK_DIV_SHIFT = 0,
90 MCU_CLK_DIV_MASK = GENMASK(4, 0),
93 CLK_SARADC_DIV_CON_SHIFT = 8,
94 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
95 CLK_SARADC_DIV_CON_WIDTH = 8,
98 GMAC_MUX_SEL_EXTCLK = BIT(8),
101 MMC_PLL_SEL_SHIFT = 8,
102 MMC_PLL_SEL_MASK = GENMASK(9, 8),
103 MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT),
104 MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT),
105 MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT),
106 MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT),
107 MMC_CLK_DIV_SHIFT = 0,
108 MMC_CLK_DIV_MASK = GENMASK(6, 0),
111 MCU_PO_SRST_MASK = BIT(13),
112 MCU_SYS_SRST_MASK = BIT(12),
113 DMA1_SRST_REQ = BIT(2),
116 DMA2_SRST_REQ = BIT(0),
119 PMU_GLB_SRST_CTRL_SHIFT = 2,
120 PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2),
121 PMU_RST_BY_FST_GLB_SRST = 0,
122 PMU_RST_BY_SND_GLB_SRST = 1,
124 WDT_GLB_SRST_CTRL_SHIFT = 1,
125 WDT_GLB_SRST_CTRL_MASK = BIT(1),
126 WDT_TRIGGER_SND_GLB_SRST = 0,
127 WDT_TRIGGER_FST_GLB_SRST = 1,
128 TSADC_GLB_SRST_CTRL_SHIFT = 0,
129 TSADC_GLB_SRST_CTRL_MASK = BIT(0),
130 TSADC_TRIGGER_SND_GLB_SRST = 0,
131 TSADC_TRIGGER_FST_GLB_SRST = 1,